ipu 39 drivers/dma/ipu/ipu_idmac.c static struct ipu ipu_data; ipu 41 drivers/dma/ipu/ipu_idmac.c #define to_ipu(id) container_of(id, struct ipu, idmac) ipu 43 drivers/dma/ipu/ipu_idmac.c static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg) ipu 45 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ic + reg); ipu 48 drivers/dma/ipu/ipu_idmac.c #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF) ipu 50 drivers/dma/ipu/ipu_idmac.c static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg) ipu 52 drivers/dma/ipu/ipu_idmac.c __raw_writel(value, ipu->reg_ic + reg); ipu 55 drivers/dma/ipu/ipu_idmac.c #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF) ipu 57 drivers/dma/ipu/ipu_idmac.c static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg) ipu 59 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ipu + reg); ipu 62 drivers/dma/ipu/ipu_idmac.c static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg) ipu 64 drivers/dma/ipu/ipu_idmac.c __raw_writel(value, ipu->reg_ipu + reg); ipu 70 drivers/dma/ipu/ipu_idmac.c static void dump_idmac_reg(struct ipu *ipu) ipu 72 drivers/dma/ipu/ipu_idmac.c dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, " ipu 74 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IDMAC_CONF), ipu 75 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IC_CONF), ipu 76 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IDMAC_CHA_EN), ipu 77 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IDMAC_CHA_PRI), ipu 78 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IDMAC_CHA_BUSY)); ipu 79 drivers/dma/ipu/ipu_idmac.c dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, " ipu 81 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY), ipu 82 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY), ipu 83 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF), ipu 84 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL), ipu 85 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_TASKS_STAT)); ipu 113 drivers/dma/ipu/ipu_idmac.c static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel) ipu 127 drivers/dma/ipu/ipu_idmac.c ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask; ipu 128 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, ic_conf, IC_CONF); ipu 132 drivers/dma/ipu/ipu_idmac.c static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel) ipu 146 drivers/dma/ipu/ipu_idmac.c ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask; ipu 147 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, ic_conf, IC_CONF); ipu 150 drivers/dma/ipu/ipu_idmac.c static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel) ipu 153 drivers/dma/ipu/ipu_idmac.c uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT); ipu 508 drivers/dma/ipu/ipu_idmac.c static int ipu_ic_init_prpenc(struct ipu *ipu, ipu 536 drivers/dma/ipu/ipu_idmac.c dev_err(ipu->dev, "Colourspace conversion unsupported!\n"); ipu 540 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC); ipu 542 drivers/dma/ipu/ipu_idmac.c ic_conf = idmac_read_icreg(ipu, IC_CONF); ipu 549 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, ic_conf, IC_CONF); ipu 560 drivers/dma/ipu/ipu_idmac.c static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel, ipu 563 drivers/dma/ipu/ipu_idmac.c u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI); ipu 570 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI); ipu 572 drivers/dma/ipu/ipu_idmac.c dump_idmac_reg(ipu); ipu 604 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 609 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 612 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF); ipu 620 drivers/dma/ipu/ipu_idmac.c ipu_channel_set_priority(ipu, channel, true); ipu 625 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IDMAC_CHA_EN); ipu 627 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN); ipu 629 drivers/dma/ipu/ipu_idmac.c ipu_ic_enable_task(ipu, channel); ipu 631 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 659 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 668 drivers/dma/ipu/ipu_idmac.c dev_err(ipu->dev, ipu 676 drivers/dma/ipu/ipu_idmac.c dev_err(ipu->dev, "Stride must be 8 pixel multiple\n"); ipu 685 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 689 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL); ipu 696 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL); ipu 700 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 824 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 890 drivers/dma/ipu/ipu_idmac.c dump_idmac_reg(ipu); ipu 955 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 958 drivers/dma/ipu/ipu_idmac.c dev_dbg(ipu->dev, "init channel = %d\n", channel); ipu 964 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 969 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); ipu 970 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF); ipu 974 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW); ipu 975 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); ipu 976 drivers/dma/ipu/ipu_idmac.c ret = ipu_ic_init_prpenc(ipu, params, true); ipu 985 drivers/dma/ipu/ipu_idmac.c ipu->channel_init_mask |= 1L << channel; ipu 988 drivers/dma/ipu/ipu_idmac.c ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) | ipu 990 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, ipu_conf, IPU_CONF); ipu 992 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 997 drivers/dma/ipu/ipu_idmac.c dump_idmac_reg(ipu); ipu 1014 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 1016 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 1018 drivers/dma/ipu/ipu_idmac.c if (!(ipu->channel_init_mask & chan_mask)) { ipu 1019 drivers/dma/ipu/ipu_idmac.c dev_err(ipu->dev, "Channel already uninitialized %d\n", ipu 1021 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 1026 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL); ipu 1027 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL); ipu 1033 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); ipu 1034 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN), ipu 1038 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); ipu 1039 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1), ipu 1048 drivers/dma/ipu/ipu_idmac.c ipu->channel_init_mask &= ~(1L << channel); ipu 1050 drivers/dma/ipu/ipu_idmac.c ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) & ipu 1052 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, ipu_conf, IPU_CONF); ipu 1054 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 1073 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 1082 drivers/dma/ipu/ipu_idmac.c while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) || ipu 1083 drivers/dma/ipu/ipu_idmac.c (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) { ipu 1088 drivers/dma/ipu/ipu_idmac.c dev_dbg(ipu->dev, ipu 1092 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY), ipu 1093 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY), ipu 1094 drivers/dma/ipu/ipu_idmac.c idmac_read_icreg(ipu, IDMAC_CHA_BUSY), ipu 1095 drivers/dma/ipu/ipu_idmac.c idmac_read_ipureg(ipu, IPU_TASKS_STAT)); ipu 1099 drivers/dma/ipu/ipu_idmac.c dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout); ipu 1109 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 1112 drivers/dma/ipu/ipu_idmac.c ipu_ic_disable_task(ipu, channel); ipu 1115 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IDMAC_CHA_EN); ipu 1116 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN); ipu 1118 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 1304 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = (struct ipu *)arg; ipu 1308 drivers/dma/ipu/ipu_idmac.c struct idmac_channel *ichan = ipu->channel + i; ipu 1381 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 1385 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 1387 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 1401 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 1407 drivers/dma/ipu/ipu_idmac.c spin_lock_irqsave(&ipu->lock, flags); ipu 1408 drivers/dma/ipu/ipu_idmac.c ipu_ic_disable_task(ipu, chan->chan_id); ipu 1417 drivers/dma/ipu/ipu_idmac.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 1430 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = to_ipu(idmac); ipu 1437 drivers/dma/ipu/ipu_idmac.c tasklet_disable(&ipu->tasklet); ipu 1457 drivers/dma/ipu/ipu_idmac.c tasklet_enable(&ipu->tasklet); ipu 1608 drivers/dma/ipu/ipu_idmac.c static int __init ipu_idmac_init(struct ipu *ipu) ipu 1610 drivers/dma/ipu/ipu_idmac.c struct idmac *idmac = &ipu->idmac; ipu 1618 drivers/dma/ipu/ipu_idmac.c dma->dev = ipu->dev; ipu 1631 drivers/dma/ipu/ipu_idmac.c struct idmac_channel *ichan = ipu->channel + i; ipu 1647 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF); ipu 1652 drivers/dma/ipu/ipu_idmac.c static void ipu_idmac_exit(struct ipu *ipu) ipu 1655 drivers/dma/ipu/ipu_idmac.c struct idmac *idmac = &ipu->idmac; ipu 1658 drivers/dma/ipu/ipu_idmac.c struct idmac_channel *ichan = ipu->channel + i; ipu 1768 drivers/dma/ipu/ipu_idmac.c struct ipu *ipu = platform_get_drvdata(pdev); ipu 1770 drivers/dma/ipu/ipu_idmac.c ipu_idmac_exit(ipu); ipu 1771 drivers/dma/ipu/ipu_idmac.c ipu_irq_detach_irq(ipu, pdev); ipu 1772 drivers/dma/ipu/ipu_idmac.c clk_disable_unprepare(ipu->ipu_clk); ipu 1773 drivers/dma/ipu/ipu_idmac.c clk_put(ipu->ipu_clk); ipu 1774 drivers/dma/ipu/ipu_idmac.c iounmap(ipu->reg_ic); ipu 1775 drivers/dma/ipu/ipu_idmac.c iounmap(ipu->reg_ipu); ipu 1776 drivers/dma/ipu/ipu_idmac.c tasklet_kill(&ipu->tasklet); ipu 166 drivers/dma/ipu/ipu_intern.h extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev); ipu 167 drivers/dma/ipu/ipu_intern.h extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev); ipu 22 drivers/dma/ipu/ipu_irq.c static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg) ipu 24 drivers/dma/ipu/ipu_irq.c return __raw_readl(ipu->reg_ipu + reg); ipu 27 drivers/dma/ipu/ipu_irq.c static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg) ipu 29 drivers/dma/ipu/ipu_irq.c __raw_writel(value, ipu->reg_ipu + reg); ipu 44 drivers/dma/ipu/ipu_irq.c struct ipu *ipu; ipu 73 drivers/dma/ipu/ipu_irq.c struct ipu *ipu; ipu 109 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); ipu 111 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); ipu 132 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); ipu 134 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); ipu 154 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status); ipu 173 drivers/dma/ipu/ipu_irq.c ret = bank && ipu_read_reg(bank->ipu, bank->status) & ipu 268 drivers/dma/ipu/ipu_irq.c struct ipu *ipu = irq_desc_get_handler_data(desc); ipu 276 drivers/dma/ipu/ipu_irq.c status = ipu_read_reg(ipu, bank->status); ipu 282 drivers/dma/ipu/ipu_irq.c status &= ipu_read_reg(ipu, bank->control); ipu 314 drivers/dma/ipu/ipu_irq.c int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev) ipu 324 drivers/dma/ipu/ipu_irq.c irq_bank[i].ipu = ipu; ipu 336 drivers/dma/ipu/ipu_irq.c irq_map[i].ipu = ipu; ipu 343 drivers/dma/ipu/ipu_irq.c irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu); ipu 345 drivers/dma/ipu/ipu_irq.c irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu); ipu 347 drivers/dma/ipu/ipu_irq.c ipu->irq_base = irq_base; ipu 352 drivers/dma/ipu/ipu_irq.c void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev) ipu 356 drivers/dma/ipu/ipu_irq.c irq_base = ipu->irq_base; ipu 358 drivers/dma/ipu/ipu_irq.c irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL); ipu 360 drivers/dma/ipu/ipu_irq.c irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); ipu 53 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); ipu 55 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_prg_enable(ipu); ipu 56 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_dc_enable(ipu); ipu 85 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); ipu 95 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_dc_disable(ipu); ipu 96 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_prg_disable(ipu); ipu 337 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); ipu 340 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc); ipu 346 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->di = ipu_di_get(ipu, pdata->di); ipu 362 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); ipu 376 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0, ipu 397 drivers/gpu/drm/imx/ipuv3-crtc.c ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1], ipu 88 drivers/gpu/drm/imx/ipuv3-plane.c return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, ipu 162 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); ipu 171 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch); ipu 180 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); ipu 188 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); ipu 221 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_enable(ipu_plane->ipu); ipu 249 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_disable(ipu_plane->ipu); ipu 250 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_prg_present(ipu_plane->ipu)) ipu 323 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_soc *ipu = to_ipu_plane(plane)->ipu; ipu 330 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_prg_present(ipu)) ipu 333 drivers/gpu/drm/imx/ipuv3-plane.c return ipu_prg_format_supported(ipu, format, modifier); ipu 782 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_prg_present(ipu_plane->ipu) || !available_pres) ipu 785 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_prg_format_supported(ipu_plane->ipu, ipu 810 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_prg_present(ipu_plane->ipu) && available_pres && ipu 811 drivers/gpu/drm/imx/ipuv3-plane.c ipu_prg_format_supported(ipu_plane->ipu, ipu 825 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, ipu 843 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->ipu = ipu; ipu 847 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_prg_present(ipu)) ipu 20 drivers/gpu/drm/imx/ipuv3-plane.h struct ipu_soc *ipu; ipu 32 drivers/gpu/drm/imx/ipuv3-plane.h struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, ipu 29 drivers/gpu/ipu-v3/ipu-common.c static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) ipu 31 drivers/gpu/ipu-v3/ipu-common.c return readl(ipu->cm_reg + offset); ipu 34 drivers/gpu/ipu-v3/ipu-common.c static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) ipu 36 drivers/gpu/ipu-v3/ipu-common.c writel(value, ipu->cm_reg + offset); ipu 39 drivers/gpu/ipu-v3/ipu-common.c int ipu_get_num(struct ipu_soc *ipu) ipu 41 drivers/gpu/ipu-v3/ipu-common.c return ipu->id; ipu 45 drivers/gpu/ipu-v3/ipu-common.c void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) ipu 49 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_SRM_PRI2); ipu 53 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_SRM_PRI2); ipu 265 drivers/gpu/ipu-v3/ipu-common.c struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) ipu 269 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "%s %d\n", __func__, num); ipu 274 drivers/gpu/ipu-v3/ipu-common.c mutex_lock(&ipu->channel_lock); ipu 276 drivers/gpu/ipu-v3/ipu-common.c list_for_each_entry(channel, &ipu->channels, list) { ipu 290 drivers/gpu/ipu-v3/ipu-common.c channel->ipu = ipu; ipu 291 drivers/gpu/ipu-v3/ipu-common.c list_add(&channel->list, &ipu->channels); ipu 294 drivers/gpu/ipu-v3/ipu-common.c mutex_unlock(&ipu->channel_lock); ipu 302 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 304 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); ipu 306 drivers/gpu/ipu-v3/ipu-common.c mutex_lock(&ipu->channel_lock); ipu 311 drivers/gpu/ipu-v3/ipu-common.c mutex_unlock(&ipu->channel_lock); ipu 330 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 333 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); ipu 339 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 343 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 345 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); ipu 350 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); ipu 354 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 384 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 412 drivers/gpu/ipu-v3/ipu-common.c if (bursts && ipu->ipu_type != IPUV3H) ipu 422 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 424 drivers/gpu/ipu-v3/ipu-common.c regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); ipu 427 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); ipu 429 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 435 drivers/gpu/ipu-v3/ipu-common.c int ipu_module_enable(struct ipu_soc *ipu, u32 mask) ipu 440 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, lock_flags); ipu 442 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_DISP_GEN); ipu 449 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_DISP_GEN); ipu 451 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); ipu 453 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); ipu 455 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, lock_flags); ipu 461 drivers/gpu/ipu-v3/ipu-common.c int ipu_module_disable(struct ipu_soc *ipu, u32 mask) ipu 466 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, lock_flags); ipu 468 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); ipu 470 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); ipu 472 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_DISP_GEN); ipu 479 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_DISP_GEN); ipu 481 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, lock_flags); ipu 489 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 492 drivers/gpu/ipu-v3/ipu-common.c return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; ipu 498 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 502 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 505 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); ipu 508 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); ipu 511 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); ipu 514 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 522 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 526 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 530 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); ipu 532 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); ipu 534 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 540 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 544 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 546 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ ipu 549 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); ipu 552 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); ipu 555 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); ipu 560 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ ipu 562 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 568 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 572 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 574 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); ipu 576 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); ipu 578 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 584 drivers/gpu/ipu-v3/ipu-common.c bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) ipu 586 drivers/gpu/ipu-v3/ipu-common.c return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); ipu 592 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 596 drivers/gpu/ipu-v3/ipu-common.c while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & ipu 609 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 613 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 616 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); ipu 618 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); ipu 623 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ ipu 625 drivers/gpu/ipu-v3/ipu-common.c if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & ipu 627 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(channel->num), ipu 631 drivers/gpu/ipu-v3/ipu-common.c if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & ipu 633 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, idma_mask(channel->num), ipu 637 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ ipu 640 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); ipu 642 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); ipu 644 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 658 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = channel->ipu; ipu 662 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 664 drivers/gpu/ipu-v3/ipu-common.c val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); ipu 669 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); ipu 671 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 675 drivers/gpu/ipu-v3/ipu-common.c static int ipu_memory_reset(struct ipu_soc *ipu) ipu 679 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); ipu 682 drivers/gpu/ipu-v3/ipu-common.c while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { ipu 695 drivers/gpu/ipu-v3/ipu-common.c void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) ipu 703 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 705 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); ipu 710 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); ipu 712 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 719 drivers/gpu/ipu-v3/ipu-common.c void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) ipu 724 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 726 drivers/gpu/ipu-v3/ipu-common.c val = ipu_cm_read(ipu, IPU_CONF); ipu 737 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, val, IPU_CONF); ipu 739 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 797 drivers/gpu/ipu-v3/ipu-common.c int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) ipu 807 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 810 drivers/gpu/ipu-v3/ipu-common.c src_reg = ipu_cm_read(ipu, link->src.reg); ipu 813 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, src_reg, link->src.reg); ipu 817 drivers/gpu/ipu-v3/ipu-common.c sink_reg = ipu_cm_read(ipu, link->sink.reg); ipu 820 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, sink_reg, link->sink.reg); ipu 823 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 831 drivers/gpu/ipu-v3/ipu-common.c int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) ipu 841 drivers/gpu/ipu-v3/ipu-common.c spin_lock_irqsave(&ipu->lock, flags); ipu 844 drivers/gpu/ipu-v3/ipu-common.c src_reg = ipu_cm_read(ipu, link->src.reg); ipu 846 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, src_reg, link->src.reg); ipu 850 drivers/gpu/ipu-v3/ipu-common.c sink_reg = ipu_cm_read(ipu, link->sink.reg); ipu 852 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, sink_reg, link->sink.reg); ipu 855 drivers/gpu/ipu-v3/ipu-common.c spin_unlock_irqrestore(&ipu->lock, flags); ipu 863 drivers/gpu/ipu-v3/ipu-common.c return ipu_fsu_link(src->ipu, src->num, sink->num); ipu 870 drivers/gpu/ipu-v3/ipu-common.c return ipu_fsu_unlink(src->ipu, src->num, sink->num); ipu 947 drivers/gpu/ipu-v3/ipu-common.c static int ipu_submodules_init(struct ipu_soc *ipu, ipu 954 drivers/gpu/ipu-v3/ipu-common.c const struct ipu_devtype *devtype = ipu->devtype; ipu 956 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); ipu 962 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, ipu 969 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, ipu 976 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_ic_init(ipu, dev, ipu 984 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, ipu 992 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_image_convert_init(ipu, dev); ipu 998 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, ipu 1005 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, ipu 1012 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + ipu 1019 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_dmfc_init(ipu, dev, ipu_base + ipu 1026 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); ipu 1032 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_smfc_init(ipu, dev, ipu_base + ipu 1042 drivers/gpu/ipu-v3/ipu-common.c ipu_dp_exit(ipu); ipu 1044 drivers/gpu/ipu-v3/ipu-common.c ipu_dmfc_exit(ipu); ipu 1046 drivers/gpu/ipu-v3/ipu-common.c ipu_dc_exit(ipu); ipu 1048 drivers/gpu/ipu-v3/ipu-common.c ipu_di_exit(ipu, 1); ipu 1050 drivers/gpu/ipu-v3/ipu-common.c ipu_di_exit(ipu, 0); ipu 1052 drivers/gpu/ipu-v3/ipu-common.c ipu_image_convert_exit(ipu); ipu 1054 drivers/gpu/ipu-v3/ipu-common.c ipu_vdi_exit(ipu); ipu 1056 drivers/gpu/ipu-v3/ipu-common.c ipu_ic_exit(ipu); ipu 1058 drivers/gpu/ipu-v3/ipu-common.c ipu_csi_exit(ipu, 1); ipu 1060 drivers/gpu/ipu-v3/ipu-common.c ipu_csi_exit(ipu, 0); ipu 1062 drivers/gpu/ipu-v3/ipu-common.c ipu_cpmem_exit(ipu); ipu 1068 drivers/gpu/ipu-v3/ipu-common.c static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) ipu 1075 drivers/gpu/ipu-v3/ipu-common.c status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); ipu 1076 drivers/gpu/ipu-v3/ipu-common.c status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); ipu 1079 drivers/gpu/ipu-v3/ipu-common.c irq = irq_linear_revmap(ipu->domain, ipu 1089 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = irq_desc_get_handler_data(desc); ipu 1095 drivers/gpu/ipu-v3/ipu-common.c ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); ipu 1102 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = irq_desc_get_handler_data(desc); ipu 1108 drivers/gpu/ipu-v3/ipu-common.c ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); ipu 1113 drivers/gpu/ipu-v3/ipu-common.c int ipu_map_irq(struct ipu_soc *ipu, int irq) ipu 1117 drivers/gpu/ipu-v3/ipu-common.c virq = irq_linear_revmap(ipu->domain, irq); ipu 1119 drivers/gpu/ipu-v3/ipu-common.c virq = irq_create_mapping(ipu->domain, irq); ipu 1125 drivers/gpu/ipu-v3/ipu-common.c int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, ipu 1128 drivers/gpu/ipu-v3/ipu-common.c return ipu_map_irq(ipu, irq_type + channel->num); ipu 1132 drivers/gpu/ipu-v3/ipu-common.c static void ipu_submodules_exit(struct ipu_soc *ipu) ipu 1134 drivers/gpu/ipu-v3/ipu-common.c ipu_smfc_exit(ipu); ipu 1135 drivers/gpu/ipu-v3/ipu-common.c ipu_dp_exit(ipu); ipu 1136 drivers/gpu/ipu-v3/ipu-common.c ipu_dmfc_exit(ipu); ipu 1137 drivers/gpu/ipu-v3/ipu-common.c ipu_dc_exit(ipu); ipu 1138 drivers/gpu/ipu-v3/ipu-common.c ipu_di_exit(ipu, 1); ipu 1139 drivers/gpu/ipu-v3/ipu-common.c ipu_di_exit(ipu, 0); ipu 1140 drivers/gpu/ipu-v3/ipu-common.c ipu_image_convert_exit(ipu); ipu 1141 drivers/gpu/ipu-v3/ipu-common.c ipu_vdi_exit(ipu); ipu 1142 drivers/gpu/ipu-v3/ipu-common.c ipu_ic_exit(ipu); ipu 1143 drivers/gpu/ipu-v3/ipu-common.c ipu_csi_exit(ipu, 1); ipu 1144 drivers/gpu/ipu-v3/ipu-common.c ipu_csi_exit(ipu, 0); ipu 1145 drivers/gpu/ipu-v3/ipu-common.c ipu_cpmem_exit(ipu); ipu 1207 drivers/gpu/ipu-v3/ipu-common.c static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) ipu 1209 drivers/gpu/ipu-v3/ipu-common.c struct device *dev = ipu->dev; ipu 1261 drivers/gpu/ipu-v3/ipu-common.c static int ipu_irq_init(struct ipu_soc *ipu) ipu 1277 drivers/gpu/ipu-v3/ipu-common.c ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, ipu 1278 drivers/gpu/ipu-v3/ipu-common.c &irq_generic_chip_ops, ipu); ipu 1279 drivers/gpu/ipu-v3/ipu-common.c if (!ipu->domain) { ipu 1280 drivers/gpu/ipu-v3/ipu-common.c dev_err(ipu->dev, "failed to add irq domain\n"); ipu 1284 drivers/gpu/ipu-v3/ipu-common.c ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", ipu 1287 drivers/gpu/ipu-v3/ipu-common.c dev_err(ipu->dev, "failed to alloc generic irq chips\n"); ipu 1288 drivers/gpu/ipu-v3/ipu-common.c irq_domain_remove(ipu->domain); ipu 1294 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); ipu 1295 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); ipu 1299 drivers/gpu/ipu-v3/ipu-common.c gc = irq_get_domain_generic_chip(ipu->domain, i); ipu 1300 drivers/gpu/ipu-v3/ipu-common.c gc->reg_base = ipu->cm_reg; ipu 1310 drivers/gpu/ipu-v3/ipu-common.c irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); ipu 1311 drivers/gpu/ipu-v3/ipu-common.c irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, ipu 1312 drivers/gpu/ipu-v3/ipu-common.c ipu); ipu 1317 drivers/gpu/ipu-v3/ipu-common.c static void ipu_irq_exit(struct ipu_soc *ipu) ipu 1321 drivers/gpu/ipu-v3/ipu-common.c irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); ipu 1322 drivers/gpu/ipu-v3/ipu-common.c irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); ipu 1327 drivers/gpu/ipu-v3/ipu-common.c irq = irq_linear_revmap(ipu->domain, i); ipu 1332 drivers/gpu/ipu-v3/ipu-common.c irq_domain_remove(ipu->domain); ipu 1335 drivers/gpu/ipu-v3/ipu-common.c void ipu_dump(struct ipu_soc *ipu) ipu 1339 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu 1340 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_CONF)); ipu 1341 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu 1342 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_CONF)); ipu 1343 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", ipu 1344 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); ipu 1345 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", ipu 1346 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); ipu 1347 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", ipu 1348 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); ipu 1349 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", ipu 1350 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); ipu 1351 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", ipu 1352 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); ipu 1353 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", ipu 1354 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); ipu 1355 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", ipu 1356 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); ipu 1357 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", ipu 1358 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); ipu 1359 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", ipu 1360 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); ipu 1361 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", ipu 1362 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); ipu 1363 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", ipu 1364 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); ipu 1365 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", ipu 1366 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); ipu 1368 drivers/gpu/ipu-v3/ipu-common.c dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, ipu 1369 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_read(ipu, IPU_INT_CTRL(i))); ipu 1376 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu; ipu 1398 drivers/gpu/ipu-v3/ipu-common.c ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); ipu 1399 drivers/gpu/ipu-v3/ipu-common.c if (!ipu) ipu 1402 drivers/gpu/ipu-v3/ipu-common.c ipu->id = of_alias_get_id(np, "ipu"); ipu 1403 drivers/gpu/ipu-v3/ipu-common.c if (ipu->id < 0) ipu 1404 drivers/gpu/ipu-v3/ipu-common.c ipu->id = 0; ipu 1408 drivers/gpu/ipu-v3/ipu-common.c ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, ipu 1409 drivers/gpu/ipu-v3/ipu-common.c "fsl,prg", ipu->id); ipu 1410 drivers/gpu/ipu-v3/ipu-common.c if (!ipu->prg_priv) ipu 1414 drivers/gpu/ipu-v3/ipu-common.c ipu->devtype = devtype; ipu 1415 drivers/gpu/ipu-v3/ipu-common.c ipu->ipu_type = devtype->type; ipu 1417 drivers/gpu/ipu-v3/ipu-common.c spin_lock_init(&ipu->lock); ipu 1418 drivers/gpu/ipu-v3/ipu-common.c mutex_init(&ipu->channel_lock); ipu 1419 drivers/gpu/ipu-v3/ipu-common.c INIT_LIST_HEAD(&ipu->channels); ipu 1450 drivers/gpu/ipu-v3/ipu-common.c ipu->cm_reg = devm_ioremap(&pdev->dev, ipu 1452 drivers/gpu/ipu-v3/ipu-common.c ipu->idmac_reg = devm_ioremap(&pdev->dev, ipu 1456 drivers/gpu/ipu-v3/ipu-common.c if (!ipu->cm_reg || !ipu->idmac_reg) ipu 1459 drivers/gpu/ipu-v3/ipu-common.c ipu->clk = devm_clk_get(&pdev->dev, "bus"); ipu 1460 drivers/gpu/ipu-v3/ipu-common.c if (IS_ERR(ipu->clk)) { ipu 1461 drivers/gpu/ipu-v3/ipu-common.c ret = PTR_ERR(ipu->clk); ipu 1466 drivers/gpu/ipu-v3/ipu-common.c platform_set_drvdata(pdev, ipu); ipu 1468 drivers/gpu/ipu-v3/ipu-common.c ret = clk_prepare_enable(ipu->clk); ipu 1474 drivers/gpu/ipu-v3/ipu-common.c ipu->dev = &pdev->dev; ipu 1475 drivers/gpu/ipu-v3/ipu-common.c ipu->irq_sync = irq_sync; ipu 1476 drivers/gpu/ipu-v3/ipu-common.c ipu->irq_err = irq_err; ipu 1483 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_memory_reset(ipu); ipu 1487 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_irq_init(ipu); ipu 1492 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), ipu 1495 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); ipu 1499 drivers/gpu/ipu-v3/ipu-common.c ret = ipu_add_client_devices(ipu, ipu_base); ipu 1511 drivers/gpu/ipu-v3/ipu-common.c ipu_submodules_exit(ipu); ipu 1513 drivers/gpu/ipu-v3/ipu-common.c ipu_irq_exit(ipu); ipu 1516 drivers/gpu/ipu-v3/ipu-common.c clk_disable_unprepare(ipu->clk); ipu 1522 drivers/gpu/ipu-v3/ipu-common.c struct ipu_soc *ipu = platform_get_drvdata(pdev); ipu 1525 drivers/gpu/ipu-v3/ipu-common.c ipu_submodules_exit(ipu); ipu 1526 drivers/gpu/ipu-v3/ipu-common.c ipu_irq_exit(ipu); ipu 1528 drivers/gpu/ipu-v3/ipu-common.c clk_disable_unprepare(ipu->clk); ipu 27 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_soc *ipu; ipu 95 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; ipu 260 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_soc *ipu = ch->ipu; ipu 263 drivers/gpu/ipu-v3/ipu-cpmem.c if (ipu->ipu_type == IPUV3EX) ipu 266 drivers/gpu/ipu-v3/ipu-cpmem.c val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num)); ipu 268 drivers/gpu/ipu-v3/ipu-cpmem.c ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num)); ipu 624 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_soc *ipu = ch->ipu; ipu 636 drivers/gpu/ipu-v3/ipu-cpmem.c val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA); ipu 638 drivers/gpu/ipu-v3/ipu-cpmem.c ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA); ipu 892 drivers/gpu/ipu-v3/ipu-cpmem.c struct ipu_soc *ipu = ch->ipu; ipu 895 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno, ipu 901 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno, ipu 907 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "PFS 0x%x, ", ipu 909 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "BPP 0x%x, ", ipu 911 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "NPB 0x%x\n", ipu 914 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "FW %d, ", ipu 916 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "FH %d, ", ipu 918 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "EBA0 0x%x\n", ipu 920 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "EBA1 0x%x\n", ipu 922 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Stride %d\n", ipu 924 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "scan_order %d\n", ipu 926 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "uv_stride %d\n", ipu 928 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "u_offset 0x%x\n", ipu 930 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "v_offset 0x%x\n", ipu 933 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Width0 %d+1, ", ipu 935 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Width1 %d+1, ", ipu 937 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Width2 %d+1, ", ipu 939 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Width3 %d+1, ", ipu 941 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Offset0 %d, ", ipu 943 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Offset1 %d, ", ipu 945 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Offset2 %d, ", ipu 947 drivers/gpu/ipu-v3/ipu-cpmem.c dev_dbg(ipu->dev, "Offset3 %d\n", ipu 952 drivers/gpu/ipu-v3/ipu-cpmem.c int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) ipu 960 drivers/gpu/ipu-v3/ipu-cpmem.c ipu->cpmem_priv = cpmem; ipu 969 drivers/gpu/ipu-v3/ipu-cpmem.c cpmem->ipu = ipu; ipu 974 drivers/gpu/ipu-v3/ipu-cpmem.c void ipu_cpmem_exit(struct ipu_soc *ipu) ipu 29 drivers/gpu/ipu-v3/ipu-csi.c struct ipu_soc *ipu; ipu 201 drivers/gpu/ipu-v3/ipu-csi.c dev_err(csi->ipu->dev, ipu 413 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "capture field swap\n"); ipu 480 drivers/gpu/ipu-v3/ipu-csi.c dev_err(csi->ipu->dev, ipu 508 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n", ipu 510 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", ipu 544 drivers/gpu/ipu-v3/ipu-csi.c dev_err(csi->ipu->dev, ipu 716 drivers/gpu/ipu-v3/ipu-csi.c ipu_module_enable(csi->ipu, csi->module); ipu 724 drivers/gpu/ipu-v3/ipu-csi.c ipu_module_disable(csi->ipu, csi->module); ipu 730 drivers/gpu/ipu-v3/ipu-csi.c struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id) ipu 738 drivers/gpu/ipu-v3/ipu-csi.c csi = ipu->csi_priv[id]; ipu 765 drivers/gpu/ipu-v3/ipu-csi.c int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id, ipu 777 drivers/gpu/ipu-v3/ipu-csi.c ipu->csi_priv[id] = csi; ipu 789 drivers/gpu/ipu-v3/ipu-csi.c csi->ipu = ipu; ipu 794 drivers/gpu/ipu-v3/ipu-csi.c void ipu_csi_exit(struct ipu_soc *ipu, int id) ipu 800 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n", ipu 802 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n", ipu 804 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n", ipu 806 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n", ipu 808 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n", ipu 810 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n", ipu 812 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n", ipu 814 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n", ipu 816 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n", ipu 818 drivers/gpu/ipu-v3/ipu-csi.c dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n", ipu 101 drivers/gpu/ipu-v3/ipu-dc.c struct ipu_soc *ipu; ipu 226 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_enable(struct ipu_soc *ipu) ipu 228 drivers/gpu/ipu-v3/ipu-dc.c struct ipu_dc_priv *priv = ipu->dc_priv; ipu 233 drivers/gpu/ipu-v3/ipu-dc.c ipu_module_enable(priv->ipu, IPU_CONF_DC_EN); ipu 261 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_disable(struct ipu_soc *ipu) ipu 263 drivers/gpu/ipu-v3/ipu-dc.c struct ipu_dc_priv *priv = ipu->dc_priv; ipu 269 drivers/gpu/ipu-v3/ipu-dc.c ipu_module_disable(priv->ipu, IPU_CONF_DC_EN); ipu 303 drivers/gpu/ipu-v3/ipu-dc.c struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel) ipu 305 drivers/gpu/ipu-v3/ipu-dc.c struct ipu_dc_priv *priv = ipu->dc_priv; ipu 338 drivers/gpu/ipu-v3/ipu-dc.c int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, ipu 353 drivers/gpu/ipu-v3/ipu-dc.c priv->ipu = ipu; ipu 374 drivers/gpu/ipu-v3/ipu-dc.c ipu->dc_priv = priv; ipu 418 drivers/gpu/ipu-v3/ipu-dc.c void ipu_dc_exit(struct ipu_soc *ipu) ipu 25 drivers/gpu/ipu-v3/ipu-di.c struct ipu_soc *ipu; ipu 170 drivers/gpu/ipu-v3/ipu-di.c dev_err(di->ipu->dev, "DI%d counters out of range.\n", ipu 454 drivers/gpu/ipu-v3/ipu-di.c dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n", ipu 497 drivers/gpu/ipu-v3/ipu-di.c dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n", ipu 525 drivers/gpu/ipu-v3/ipu-di.c dev_warn(di->ipu->dev, "failed to adjust videomode\n"); ipu 529 drivers/gpu/ipu-v3/ipu-di.c dev_dbg(di->ipu->dev, "videomode adapted for IPU restrictions\n"); ipu 563 drivers/gpu/ipu-v3/ipu-di.c dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n", ipu 566 drivers/gpu/ipu-v3/ipu-di.c dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n", ipu 647 drivers/gpu/ipu-v3/ipu-di.c ipu_module_enable(di->ipu, di->module); ipu 657 drivers/gpu/ipu-v3/ipu-di.c ipu_module_disable(di->ipu, di->module); ipu 673 drivers/gpu/ipu-v3/ipu-di.c struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) ipu 680 drivers/gpu/ipu-v3/ipu-di.c di = ipu->di_priv[disp]; ipu 707 drivers/gpu/ipu-v3/ipu-di.c int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, ipu 720 drivers/gpu/ipu-v3/ipu-di.c ipu->di_priv[id] = di; ipu 738 drivers/gpu/ipu-v3/ipu-di.c di->ipu = ipu; ipu 743 drivers/gpu/ipu-v3/ipu-di.c void ipu_di_exit(struct ipu_soc *ipu, int id) ipu 87 drivers/gpu/ipu-v3/ipu-dmfc.c struct ipu_soc *ipu; ipu 93 drivers/gpu/ipu-v3/ipu-dmfc.c struct ipu_soc *ipu; ipu 107 drivers/gpu/ipu-v3/ipu-dmfc.c ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN); ipu 126 drivers/gpu/ipu-v3/ipu-dmfc.c ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN); ipu 155 drivers/gpu/ipu-v3/ipu-dmfc.c struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel) ipu 157 drivers/gpu/ipu-v3/ipu-dmfc.c struct ipu_dmfc_priv *priv = ipu->dmfc_priv; ipu 172 drivers/gpu/ipu-v3/ipu-dmfc.c int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, ipu 187 drivers/gpu/ipu-v3/ipu-dmfc.c priv->ipu = ipu; ipu 190 drivers/gpu/ipu-v3/ipu-dmfc.c ipu->dmfc_priv = priv; ipu 194 drivers/gpu/ipu-v3/ipu-dmfc.c priv->channels[i].ipu = ipu; ipu 212 drivers/gpu/ipu-v3/ipu-dmfc.c void ipu_dmfc_exit(struct ipu_soc *ipu) ipu 60 drivers/gpu/ipu-v3/ipu-dp.c struct ipu_soc *ipu; ipu 106 drivers/gpu/ipu-v3/ipu-dp.c ipu_srm_dp_update(priv->ipu, true); ipu 121 drivers/gpu/ipu-v3/ipu-dp.c ipu_srm_dp_update(priv->ipu, true); ipu 202 drivers/gpu/ipu-v3/ipu-dp.c ipu_srm_dp_update(priv->ipu, true); ipu 210 drivers/gpu/ipu-v3/ipu-dp.c int ipu_dp_enable(struct ipu_soc *ipu) ipu 212 drivers/gpu/ipu-v3/ipu-dp.c struct ipu_dp_priv *priv = ipu->dp_priv; ipu 217 drivers/gpu/ipu-v3/ipu-dp.c ipu_module_enable(priv->ipu, IPU_CONF_DP_EN); ipu 242 drivers/gpu/ipu-v3/ipu-dp.c ipu_srm_dp_update(priv->ipu, true); ipu 273 drivers/gpu/ipu-v3/ipu-dp.c ipu_srm_dp_update(priv->ipu, sync); ipu 279 drivers/gpu/ipu-v3/ipu-dp.c void ipu_dp_disable(struct ipu_soc *ipu) ipu 281 drivers/gpu/ipu-v3/ipu-dp.c struct ipu_dp_priv *priv = ipu->dp_priv; ipu 288 drivers/gpu/ipu-v3/ipu-dp.c ipu_module_disable(priv->ipu, IPU_CONF_DP_EN); ipu 297 drivers/gpu/ipu-v3/ipu-dp.c struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow) ipu 299 drivers/gpu/ipu-v3/ipu-dp.c struct ipu_dp_priv *priv = ipu->dp_priv; ipu 325 drivers/gpu/ipu-v3/ipu-dp.c int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base) ipu 334 drivers/gpu/ipu-v3/ipu-dp.c priv->ipu = ipu; ipu 336 drivers/gpu/ipu-v3/ipu-dp.c ipu->dp_priv = priv; ipu 355 drivers/gpu/ipu-v3/ipu-dp.c void ipu_dp_exit(struct ipu_soc *ipu) ipu 158 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_soc *ipu; ipu 222 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_soc *ipu = priv->ipu; ipu 230 drivers/gpu/ipu-v3/ipu-ic.c dev_err(ipu->dev, "Unsupported resize (in_size > 4096)\n"); ipu 234 drivers/gpu/ipu-v3/ipu-ic.c dev_err(ipu->dev, "Unsupported resize (out_size > 1024)\n"); ipu 240 drivers/gpu/ipu-v3/ipu-ic.c dev_err(ipu->dev, "Unsupported downsize\n"); ipu 261 drivers/gpu/ipu-v3/ipu-ic.c dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n"); ipu 457 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_soc *ipu = priv->ipu; ipu 465 drivers/gpu/ipu-v3/ipu-ic.c dev_err(ipu->dev, "Illegal burst length for IC\n"); ipu 597 drivers/gpu/ipu-v3/ipu-ic.c ipu_module_enable(priv->ipu, IPU_CONF_ROT_EN); ipu 608 drivers/gpu/ipu-v3/ipu-ic.c ipu_module_disable(priv->ipu, IPU_CONF_ROT_EN); ipu 620 drivers/gpu/ipu-v3/ipu-ic.c ipu_module_enable(priv->ipu, IPU_CONF_IC_EN); ipu 643 drivers/gpu/ipu-v3/ipu-ic.c ipu_module_disable(priv->ipu, IPU_CONF_IC_EN); ipu 659 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task) ipu 661 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_ic_priv *priv = ipu->ic_priv; ipu 697 drivers/gpu/ipu-v3/ipu-ic.c int ipu_ic_init(struct ipu_soc *ipu, struct device *dev, ipu 707 drivers/gpu/ipu-v3/ipu-ic.c ipu->ic_priv = priv; ipu 719 drivers/gpu/ipu-v3/ipu-ic.c priv->ipu = ipu; ipu 731 drivers/gpu/ipu-v3/ipu-ic.c void ipu_ic_exit(struct ipu_soc *ipu) ipu 738 drivers/gpu/ipu-v3/ipu-ic.c struct ipu_soc *ipu = priv->ipu; ipu 740 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_CONF = \t0x%08X\n", ipu 742 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_PRP_ENC_RSC = \t0x%08X\n", ipu 744 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_PRP_VF_RSC = \t0x%08X\n", ipu 746 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_PP_RSC = \t0x%08X\n", ipu 748 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_CMBP_1 = \t0x%08X\n", ipu 750 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_CMBP_2 = \t0x%08X\n", ipu 752 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_IDMAC_1 = \t0x%08X\n", ipu 754 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_IDMAC_2 = \t0x%08X\n", ipu 756 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_IDMAC_3 = \t0x%08X\n", ipu 758 drivers/gpu/ipu-v3/ipu-ic.c dev_dbg(ipu->dev, "IC_IDMAC_4 = \t0x%08X\n", ipu 210 drivers/gpu/ipu-v3/ipu-image-convert.c struct ipu_soc *ipu; ipu 327 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 357 drivers/gpu/ipu-v3/ipu-image-convert.c dma_free_coherent(priv->ipu->dev, ipu 368 drivers/gpu/ipu-v3/ipu-image-convert.c buf->virt = dma_alloc_coherent(priv->ipu->dev, buf->len, &buf->phys, ipu 371 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "failed to alloc dma buffer\n"); ipu 442 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(ctx->chan->priv->ipu->dev, ipu 495 drivers/gpu/ipu-v3/ipu-image-convert.c struct device *dev = ctx->chan->priv->ipu->dev; ipu 719 drivers/gpu/ipu-v3/ipu-image-convert.c struct device *dev = ctx->chan->priv->ipu->dev; ipu 877 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 886 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "invalid %s tile size: %ux%u\n", ipu 937 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n", ipu 1019 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, ipu 1061 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, ipu 1139 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: column %u hscale: *8192/%u\n", ipu 1196 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: row %u vscale: *8192/%u\n", ipu 1260 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: stopping ctx %p run %p\n", ipu 1361 drivers/gpu/ipu-v3/ipu-image-convert.c if (!channel->ipu->prg_priv) ipu 1380 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: starting ctx %p run %p tile %u -> %u\n", ipu 1400 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n", ipu 1412 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "ipu_ic_task_init failed, %d\n", ret); ipu 1473 drivers/gpu/ipu-v3/ipu-image-convert.c ipu_dump(priv->ipu); ipu 1511 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 1547 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 1571 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: enter\n", __func__, ipu 1584 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 1593 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: exit\n", __func__, ipu 1765 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "Unexpected rotation interrupt\n"); ipu 1832 drivers/gpu/ipu-v3/ipu-image-convert.c chan->ic = ipu_ic_get(priv->ipu, chan->ic_task); ipu 1834 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "could not acquire IC\n"); ipu 1840 drivers/gpu/ipu-v3/ipu-image-convert.c chan->in_chan = ipu_idmac_get(priv->ipu, dma->in); ipu 1841 drivers/gpu/ipu-v3/ipu-image-convert.c chan->out_chan = ipu_idmac_get(priv->ipu, dma->out); ipu 1843 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "could not acquire idmac channels\n"); ipu 1848 drivers/gpu/ipu-v3/ipu-image-convert.c chan->rotation_in_chan = ipu_idmac_get(priv->ipu, dma->rot_in); ipu 1849 drivers/gpu/ipu-v3/ipu-image-convert.c chan->rotation_out_chan = ipu_idmac_get(priv->ipu, dma->rot_out); ipu 1851 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, ipu 1858 drivers/gpu/ipu-v3/ipu-image-convert.c chan->out_eof_irq = ipu_idmac_channel_irq(priv->ipu, ipu 1865 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "could not acquire irq %d\n", ipu 1871 drivers/gpu/ipu-v3/ipu-image-convert.c chan->rot_out_eof_irq = ipu_idmac_channel_irq(priv->ipu, ipu 1878 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "could not acquire irq %d\n", ipu 1902 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "pixelformat not supported for %s\n", ipu 2038 drivers/gpu/ipu-v3/ipu-image-convert.c ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 2044 drivers/gpu/ipu-v3/ipu-image-convert.c struct ipu_image_convert_priv *priv = ipu->image_convert_priv; ipu 2061 drivers/gpu/ipu-v3/ipu-image-convert.c dev_err(priv->ipu->dev, "%s: in/out formats invalid\n", ipu 2072 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p\n", __func__, ipu 2249 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: ctx %p run %p\n", __func__, ipu 2305 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 2316 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, ipu 2323 drivers/gpu/ipu-v3/ipu-image-convert.c dev_warn(priv->ipu->dev, "%s: timeout\n", __func__); ipu 2346 drivers/gpu/ipu-v3/ipu-image-convert.c dev_dbg(priv->ipu->dev, "%s: task %u: removing ctx %p\n", __func__, ipu 2373 drivers/gpu/ipu-v3/ipu-image-convert.c ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 2383 drivers/gpu/ipu-v3/ipu-image-convert.c ctx = ipu_image_convert_prepare(ipu, ic_task, in, out, rot_mode, ipu 2418 drivers/gpu/ipu-v3/ipu-image-convert.c int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 2428 drivers/gpu/ipu-v3/ipu-image-convert.c run = ipu_image_convert(ipu, ic_task, in, out, rot_mode, ipu 2443 drivers/gpu/ipu-v3/ipu-image-convert.c int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev) ipu 2452 drivers/gpu/ipu-v3/ipu-image-convert.c ipu->image_convert_priv = priv; ipu 2453 drivers/gpu/ipu-v3/ipu-image-convert.c priv->ipu = ipu; ipu 2473 drivers/gpu/ipu-v3/ipu-image-convert.c void ipu_image_convert_exit(struct ipu_soc *ipu) ipu 115 drivers/gpu/ipu-v3/ipu-prg.c bool ipu_prg_present(struct ipu_soc *ipu) ipu 117 drivers/gpu/ipu-v3/ipu-prg.c if (ipu->prg_priv) ipu 124 drivers/gpu/ipu-v3/ipu-prg.c bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, ipu 143 drivers/gpu/ipu-v3/ipu-prg.c int ipu_prg_enable(struct ipu_soc *ipu) ipu 145 drivers/gpu/ipu-v3/ipu-prg.c struct ipu_prg *prg = ipu->prg_priv; ipu 154 drivers/gpu/ipu-v3/ipu-prg.c void ipu_prg_disable(struct ipu_soc *ipu) ipu 156 drivers/gpu/ipu-v3/ipu-prg.c struct ipu_prg *prg = ipu->prg_priv; ipu 245 drivers/gpu/ipu-v3/ipu-prg.c struct ipu_prg *prg = ipu_chan->ipu->prg_priv; ipu 279 drivers/gpu/ipu-v3/ipu-prg.c struct ipu_prg *prg = ipu_chan->ipu->prg_priv; ipu 345 drivers/gpu/ipu-v3/ipu-prg.c struct ipu_prg *prg = ipu_chan->ipu->prg_priv; ipu 151 drivers/gpu/ipu-v3/ipu-prv.h struct ipu_soc *ipu; ipu 202 drivers/gpu/ipu-v3/ipu-prv.h static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset) ipu 204 drivers/gpu/ipu-v3/ipu-prv.h return readl(ipu->idmac_reg + offset); ipu 207 drivers/gpu/ipu-v3/ipu-prv.h static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value, ipu 210 drivers/gpu/ipu-v3/ipu-prv.h writel(value, ipu->idmac_reg + offset); ipu 213 drivers/gpu/ipu-v3/ipu-prv.h void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync); ipu 215 drivers/gpu/ipu-v3/ipu-prv.h int ipu_module_enable(struct ipu_soc *ipu, u32 mask); ipu 216 drivers/gpu/ipu-v3/ipu-prv.h int ipu_module_disable(struct ipu_soc *ipu, u32 mask); ipu 218 drivers/gpu/ipu-v3/ipu-prv.h bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno); ipu 220 drivers/gpu/ipu-v3/ipu-prv.h int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id, ipu 222 drivers/gpu/ipu-v3/ipu-prv.h void ipu_csi_exit(struct ipu_soc *ipu, int id); ipu 224 drivers/gpu/ipu-v3/ipu-prv.h int ipu_ic_init(struct ipu_soc *ipu, struct device *dev, ipu 226 drivers/gpu/ipu-v3/ipu-prv.h void ipu_ic_exit(struct ipu_soc *ipu); ipu 228 drivers/gpu/ipu-v3/ipu-prv.h int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev, ipu 230 drivers/gpu/ipu-v3/ipu-prv.h void ipu_vdi_exit(struct ipu_soc *ipu); ipu 232 drivers/gpu/ipu-v3/ipu-prv.h int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev); ipu 233 drivers/gpu/ipu-v3/ipu-prv.h void ipu_image_convert_exit(struct ipu_soc *ipu); ipu 235 drivers/gpu/ipu-v3/ipu-prv.h int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, ipu 237 drivers/gpu/ipu-v3/ipu-prv.h void ipu_di_exit(struct ipu_soc *ipu, int id); ipu 239 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, ipu 241 drivers/gpu/ipu-v3/ipu-prv.h void ipu_dmfc_exit(struct ipu_soc *ipu); ipu 243 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); ipu 244 drivers/gpu/ipu-v3/ipu-prv.h void ipu_dp_exit(struct ipu_soc *ipu); ipu 246 drivers/gpu/ipu-v3/ipu-prv.h int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, ipu 248 drivers/gpu/ipu-v3/ipu-prv.h void ipu_dc_exit(struct ipu_soc *ipu); ipu 250 drivers/gpu/ipu-v3/ipu-prv.h int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); ipu 251 drivers/gpu/ipu-v3/ipu-prv.h void ipu_cpmem_exit(struct ipu_soc *ipu); ipu 253 drivers/gpu/ipu-v3/ipu-prv.h int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); ipu 254 drivers/gpu/ipu-v3/ipu-prv.h void ipu_smfc_exit(struct ipu_soc *ipu); ipu 26 drivers/gpu/ipu-v3/ipu-smfc.c struct ipu_soc *ipu; ipu 104 drivers/gpu/ipu-v3/ipu-smfc.c ipu_module_enable(priv->ipu, IPU_CONF_SMFC_EN); ipu 124 drivers/gpu/ipu-v3/ipu-smfc.c ipu_module_disable(priv->ipu, IPU_CONF_SMFC_EN); ipu 135 drivers/gpu/ipu-v3/ipu-smfc.c struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno) ipu 137 drivers/gpu/ipu-v3/ipu-smfc.c struct ipu_smfc_priv *priv = ipu->smfc_priv; ipu 172 drivers/gpu/ipu-v3/ipu-smfc.c int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, ipu 182 drivers/gpu/ipu-v3/ipu-smfc.c ipu->smfc_priv = priv; ipu 184 drivers/gpu/ipu-v3/ipu-smfc.c priv->ipu = ipu; ipu 200 drivers/gpu/ipu-v3/ipu-smfc.c void ipu_smfc_exit(struct ipu_soc *ipu) ipu 14 drivers/gpu/ipu-v3/ipu-vdi.c struct ipu_soc *ipu; ipu 171 drivers/gpu/ipu-v3/ipu-vdi.c ipu_module_enable(vdi->ipu, vdi->module); ipu 189 drivers/gpu/ipu-v3/ipu-vdi.c ipu_module_disable(vdi->ipu, vdi->module); ipu 198 drivers/gpu/ipu-v3/ipu-vdi.c struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu) ipu 200 drivers/gpu/ipu-v3/ipu-vdi.c return ipu->vdi_priv; ipu 209 drivers/gpu/ipu-v3/ipu-vdi.c int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev, ipu 218 drivers/gpu/ipu-v3/ipu-vdi.c ipu->vdi_priv = vdi; ipu 227 drivers/gpu/ipu-v3/ipu-vdi.c vdi->ipu = ipu; ipu 232 drivers/gpu/ipu-v3/ipu-vdi.c void ipu_vdi_exit(struct ipu_soc *ipu) ipu 80 drivers/net/ipvlan/ipvlan.h } ipu; ipu 81 drivers/net/ipvlan/ipvlan.h #define ip6addr ipu.ip6 ipu 82 drivers/net/ipvlan/ipvlan.h #define ip4addr ipu.ip4 ipu 23 drivers/staging/media/imx/imx-ic-common.c struct ipu_soc *ipu, ipu 34 drivers/staging/media/imx/imx-ic-common.c priv->ipu = ipu; ipu 60 drivers/staging/media/imx/imx-ic-common.c priv->sd.grp_id, ipu_get_num(ipu)); ipu 72 drivers/staging/media/imx/imx-ic-prp.c ipu_set_ic_src_mux(ic_priv->ipu, priv->csi_id, src_is_vdic); ipu 157 drivers/staging/media/imx/imx-ic-prpencvf.c ic = ipu_ic_get(ic_priv->ipu, task); ipu 165 drivers/staging/media/imx/imx-ic-prpencvf.c out_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].out_ch); ipu 174 drivers/staging/media/imx/imx-ic-prpencvf.c rot_in_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].rot_in_ch); ipu 183 drivers/staging/media/imx/imx-ic-prpencvf.c rot_out_ch = ipu_idmac_get(ic_priv->ipu, prp_channel[task].rot_out_ch); ipu 625 drivers/staging/media/imx/imx-ic-prpencvf.c ipu_dump(ic_priv->ipu); ipu 697 drivers/staging/media/imx/imx-ic-prpencvf.c priv->nfb4eof_irq = ipu_idmac_channel_irq(ic_priv->ipu, ipu 711 drivers/staging/media/imx/imx-ic-prpencvf.c ic_priv->ipu, priv->rot_out_ch, IPU_IRQ_EOF); ipu 714 drivers/staging/media/imx/imx-ic-prpencvf.c ic_priv->ipu, priv->out_ch, IPU_IRQ_EOF); ipu 14 drivers/staging/media/imx/imx-ic.h struct ipu_soc *ipu; ipu 504 drivers/staging/media/imx/imx-media-csc-scaler.c struct ipu_soc *ipu = priv->md->ipu[0]; ipu 527 drivers/staging/media/imx/imx-media-csc-scaler.c ctx->icc = ipu_image_convert_prepare(ipu, ic_task, &in, &out, ipu 58 drivers/staging/media/imx/imx-media-csi.c struct ipu_soc *ipu; ipu 239 drivers/staging/media/imx/imx-media-csi.c smfc = ipu_smfc_get(priv->ipu, ch_num); ipu 247 drivers/staging/media/imx/imx-media-csi.c idmac_ch = ipu_idmac_get(priv->ipu, ch_num); ipu 582 drivers/staging/media/imx/imx-media-csi.c ipu_dump(priv->ipu); ipu 629 drivers/staging/media/imx/imx-media-csi.c priv->nfb4eof_irq = ipu_idmac_channel_irq(priv->ipu, ipu 641 drivers/staging/media/imx/imx-media-csi.c priv->eof_irq = ipu_idmac_channel_irq(priv->ipu, priv->idmac_ch, ipu 1146 drivers/staging/media/imx/imx-media-csi.c ipu_set_csi_src_mux(priv->ipu, priv->csi_id, is_csi2); ipu 1754 drivers/staging/media/imx/imx-media-csi.c csi = ipu_csi_get(priv->ipu, priv->csi_id); ipu 1940 drivers/staging/media/imx/imx-media-csi.c priv->ipu = dev_get_drvdata(priv->dev->parent); ipu 1964 drivers/staging/media/imx/imx-media-csi.c priv->sd.grp_id, ipu_get_num(priv->ipu)); ipu 36 drivers/staging/media/imx/imx-media-internal-sd.c struct ipu_soc *ipu, ipu 196 drivers/staging/media/imx/imx-media-internal-sd.c struct ipu_soc *ipu; ipu 199 drivers/staging/media/imx/imx-media-internal-sd.c ipu = dev_get_drvdata(ipu_dev); ipu 200 drivers/staging/media/imx/imx-media-internal-sd.c if (!ipu) { ipu 205 drivers/staging/media/imx/imx-media-internal-sd.c ipu_id = ipu_get_num(ipu); ipu 214 drivers/staging/media/imx/imx-media-internal-sd.c if (!imxmd->ipu[ipu_id]) ipu 215 drivers/staging/media/imx/imx-media-internal-sd.c imxmd->ipu[ipu_id] = ipu; ipu 231 drivers/staging/media/imx/imx-media-internal-sd.c sd = intsd->sync_register(&imxmd->v4l2_dev, ipu_dev, ipu, ipu 62 drivers/staging/media/imx/imx-media-vdic.c struct ipu_soc *ipu; ipu 140 drivers/staging/media/imx/imx-media-vdic.c vdi = ipu_vdi_get(priv->ipu); ipu 149 drivers/staging/media/imx/imx-media-vdic.c ch = ipu_idmac_get(priv->ipu, IPUV3_CHANNEL_MEM_VDI_PREV); ipu 157 drivers/staging/media/imx/imx-media-vdic.c ch = ipu_idmac_get(priv->ipu, IPUV3_CHANNEL_MEM_VDI_CUR); ipu 165 drivers/staging/media/imx/imx-media-vdic.c ch = ipu_idmac_get(priv->ipu, IPUV3_CHANNEL_MEM_VDI_NEXT); ipu 274 drivers/staging/media/imx/imx-media-vdic.c ipu_fsu_link(priv->ipu, IPUV3_CHANNEL_CSI_DIRECT, ipu 290 drivers/staging/media/imx/imx-media-vdic.c ipu_fsu_unlink(priv->ipu, IPUV3_CHANNEL_CSI_DIRECT, ipu 926 drivers/staging/media/imx/imx-media-vdic.c struct ipu_soc *ipu, ipu 937 drivers/staging/media/imx/imx-media-vdic.c priv->ipu = ipu; ipu 948 drivers/staging/media/imx/imx-media-vdic.c priv->sd.grp_id, ipu_get_num(ipu)); ipu 140 drivers/staging/media/imx/imx-media.h struct ipu_soc *ipu[2]; ipu 256 drivers/staging/media/imx/imx-media.h struct ipu_soc *ipu, ipu 263 drivers/staging/media/imx/imx-media.h struct ipu_soc *ipu, ipu 100 include/video/imx-ipu-image-convert.h ipu_image_convert_prepare(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 173 include/video/imx-ipu-image-convert.h ipu_image_convert(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 193 include/video/imx-ipu-image-convert.h int ipu_image_convert_sync(struct ipu_soc *ipu, enum ipu_ic_task ic_task, ipu 186 include/video/imx-ipu-v3.h int ipu_map_irq(struct ipu_soc *ipu, int irq); ipu 187 include/video/imx-ipu-v3.h int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, ipu 205 include/video/imx-ipu-v3.h int ipu_get_num(struct ipu_soc *ipu); ipu 206 include/video/imx-ipu-v3.h void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); ipu 207 include/video/imx-ipu-v3.h void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); ipu 208 include/video/imx-ipu-v3.h void ipu_dump(struct ipu_soc *ipu); ipu 213 include/video/imx-ipu-v3.h struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); ipu 228 include/video/imx-ipu-v3.h int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch); ipu 229 include/video/imx-ipu-v3.h int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch); ipu 286 include/video/imx-ipu-v3.h struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); ipu 290 include/video/imx-ipu-v3.h void ipu_dc_enable(struct ipu_soc *ipu); ipu 293 include/video/imx-ipu-v3.h void ipu_dc_disable(struct ipu_soc *ipu); ipu 298 include/video/imx-ipu-v3.h struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); ipu 313 include/video/imx-ipu-v3.h struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); ipu 326 include/video/imx-ipu-v3.h struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); ipu 328 include/video/imx-ipu-v3.h int ipu_dp_enable(struct ipu_soc *ipu); ipu 331 include/video/imx-ipu-v3.h void ipu_dp_disable(struct ipu_soc *ipu); ipu 342 include/video/imx-ipu-v3.h bool ipu_prg_present(struct ipu_soc *ipu); ipu 343 include/video/imx-ipu-v3.h bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format, ipu 345 include/video/imx-ipu-v3.h int ipu_prg_enable(struct ipu_soc *ipu); ipu 346 include/video/imx-ipu-v3.h void ipu_prg_disable(struct ipu_soc *ipu); ipu 376 include/video/imx-ipu-v3.h struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); ipu 457 include/video/imx-ipu-v3.h struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); ipu 471 include/video/imx-ipu-v3.h struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu); ipu 477 include/video/imx-ipu-v3.h struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);