ipp_regs          146 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs          147 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(0),
ipp_regs          148 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(1),
ipp_regs          149 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(2),
ipp_regs          150 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(3),
ipp_regs          151 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(4),
ipp_regs          152 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		ipp_regs(5)
ipp_regs          558 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          181 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs          182 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		ipp_regs(0),
ipp_regs          183 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		ipp_regs(1),
ipp_regs          184 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		ipp_regs(2)
ipp_regs          604 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          180 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs          181 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(0),
ipp_regs          182 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(1),
ipp_regs          183 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(2),
ipp_regs          184 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(3),
ipp_regs          185 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(4),
ipp_regs          186 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		ipp_regs(5)
ipp_regs          602 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          189 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs          190 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(0),
ipp_regs          191 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(1),
ipp_regs          192 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(2),
ipp_regs          193 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(3),
ipp_regs          194 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(4),
ipp_regs          195 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 		ipp_regs(5)
ipp_regs          683 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          163 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct dce_ipp_registers ipp_regs[] = {
ipp_regs          164 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(0),
ipp_regs          165 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(1),
ipp_regs          166 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(2),
ipp_regs          167 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(3),
ipp_regs          168 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(4),
ipp_regs          169 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		ipp_regs(5)
ipp_regs          726 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn10_ipp_registers ipp_regs[] = {
ipp_regs          328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	ipp_regs(0),
ipp_regs          329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	ipp_regs(1),
ipp_regs          330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	ipp_regs(2),
ipp_regs          331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	ipp_regs(3),
ipp_regs          612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          624 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn10_ipp_registers ipp_regs[] = {
ipp_regs          625 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(0),
ipp_regs          626 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(1),
ipp_regs          627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(2),
ipp_regs          628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(3),
ipp_regs          629 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(4),
ipp_regs          630 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ipp_regs(5),
ipp_regs         1003 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
ipp_regs          562 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn10_ipp_registers ipp_regs[] = {
ipp_regs          563 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	ipp_regs(0),
ipp_regs          564 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	ipp_regs(1),
ipp_regs          565 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	ipp_regs(2),
ipp_regs          566 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	ipp_regs(3),
ipp_regs          652 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			&ipp_regs[inst], &ipp_shift, &ipp_mask);