CM 173 arch/x86/mm/pat.c case PAT_UC: cache = CM(UC); cache_mode = "UC "; break; CM 174 arch/x86/mm/pat.c case PAT_WC: cache = CM(WC); cache_mode = "WC "; break; CM 175 arch/x86/mm/pat.c case PAT_WT: cache = CM(WT); cache_mode = "WT "; break; CM 176 arch/x86/mm/pat.c case PAT_WP: cache = CM(WP); cache_mode = "WP "; break; CM 177 arch/x86/mm/pat.c case PAT_WB: cache = CM(WB); cache_mode = "WB "; break; CM 178 arch/x86/mm/pat.c case PAT_UC_MINUS: cache = CM(UC_MINUS); cache_mode = "UC- "; break; CM 179 arch/x86/mm/pat.c default: cache = CM(WB); cache_mode = "WB "; break; CM 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\ CM 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\ CM 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\ CM 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\ CM 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\ CM 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\ CM 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\ CM 78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_ICSC_CONTROL, CM, id), \ CM 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_ICSC_C11_C12, CM, id), \ CM 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_ICSC_C33_C34, CM, id), \ CM 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ CM 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ CM 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ CM 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \ CM 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \ CM 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \ CM 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \ CM 88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \ CM 89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \ CM 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \ CM 91 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \ CM 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \ CM 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \ CM 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \ CM 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \ CM 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \ CM 97 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \ CM 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \ CM 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \ CM 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \ CM 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \ CM 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \ CM 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \ CM 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \ CM 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \ CM 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \ CM 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \ CM 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \ CM 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_MEM_PWR_CTRL, CM, id), \ CM 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \ CM 111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_LUT_INDEX, CM, id), \ CM 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_LUT_DATA, CM, id), \ CM 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_CONTROL, CM, id), \ CM 114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_DGAM_CONTROL, CM, id), \ CM 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_TEST_DEBUG_INDEX, CM, id), \ CM 116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_TEST_DEBUG_DATA, CM, id), \ CM 124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_HDR_MULT_COEF, CM, id) CM 130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_COMA_C11_C12, CM, id),\ CM 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_COMA_C33_C34, CM, id),\ CM 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_COMB_C11_C12, CM, id),\ CM 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_COMB_C33_C34, CM, id),\ CM 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_OCSC_CONTROL, CM, id), \ CM 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_OCSC_C11_C12, CM, id), \ CM 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_OCSC_C33_C34, CM, id), \ CM 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_BNS_VALUES_R, CM, id), \ CM 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_BNS_VALUES_G, CM, id), \ CM 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_BNS_VALUES_B, CM, id), \ CM 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_MEM_PWR_CTRL, CM, id), \ CM 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_LUT_DATA, CM, id), \ CM 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ CM 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_LUT_INDEX, CM, id), \ CM 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \ CM 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \ CM 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \ CM 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \ CM 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \ CM 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \ CM 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \ CM 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \ CM 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \ CM 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \ CM 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \ CM 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \ CM 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \ CM 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \ CM 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \ CM 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \ CM 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \ CM 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \ CM 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \ CM 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \ CM 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \ CM 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \ CM 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \ CM 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \ CM 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \ CM 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \ CM 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \ CM 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \ CM 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_RGAM_CONTROL, CM, id), \ CM 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_IGAM_CONTROL, CM, id), \ CM 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \ CM 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \ CM 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \ CM 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h SRI(CM_CMOUT_CONTROL, CM, id) CM 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \ CM 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_CONTROL, CM, id), \ CM 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \ CM 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \ CM 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_START_CNTL_R, CM, id), \ CM 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \ CM 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \ CM 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \ CM 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL1_B, CM, id), \ CM 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL2_B, CM, id), \ CM 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL1_G, CM, id), \ CM 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL2_G, CM, id), \ CM 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL1_R, CM, id), \ CM 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_END_CNTL2_R, CM, id), \ CM 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_0_1, CM, id), \ CM 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_2_3, CM, id), \ CM 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_4_5, CM, id), \ CM 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_6_7, CM, id), \ CM 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_8_9, CM, id), \ CM 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_10_11, CM, id), \ CM 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_12_13, CM, id), \ CM 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_14_15, CM, id), \ CM 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_16_17, CM, id), \ CM 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_18_19, CM, id), \ CM 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_20_21, CM, id), \ CM 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_22_23, CM, id), \ CM 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_24_25, CM, id), \ CM 62 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_26_27, CM, id), \ CM 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_28_29, CM, id), \ CM 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_30_31, CM, id), \ CM 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMB_REGION_32_33, CM, id), \ CM 66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_START_CNTL_B, CM, id), \ CM 67 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_START_CNTL_G, CM, id), \ CM 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_START_CNTL_R, CM, id), \ CM 69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \ CM 70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \ CM 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id), \ CM 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL1_B, CM, id), \ CM 73 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL2_B, CM, id), \ CM 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL1_G, CM, id), \ CM 75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL2_G, CM, id), \ CM 76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL1_R, CM, id), \ CM 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_END_CNTL2_R, CM, id), \ CM 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_0_1, CM, id), \ CM 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_2_3, CM, id), \ CM 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_4_5, CM, id), \ CM 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_6_7, CM, id), \ CM 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_8_9, CM, id), \ CM 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_10_11, CM, id), \ CM 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_12_13, CM, id), \ CM 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_14_15, CM, id), \ CM 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_16_17, CM, id), \ CM 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_18_19, CM, id), \ CM 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_20_21, CM, id), \ CM 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_22_23, CM, id), \ CM 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_24_25, CM, id), \ CM 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_26_27, CM, id), \ CM 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_28_29, CM, id), \ CM 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_30_31, CM, id), \ CM 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_RAMA_REGION_32_33, CM, id), \ CM 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_LUT_INDEX, CM, id), \ CM 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_BLNDGAM_LUT_DATA, CM, id), \ CM 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_3DLUT_MODE, CM, id), \ CM 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_3DLUT_INDEX, CM, id), \ CM 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_3DLUT_DATA, CM, id), \ CM 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_3DLUT_DATA_30BIT, CM, id), \ CM 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_3DLUT_READ_WRITE_CONTROL, CM, id), \ CM 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_LUT_WRITE_EN_MASK, CM, id), \ CM 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_CONTROL, CM, id), \ CM 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_START_CNTL_B, CM, id), \ CM 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_START_CNTL_G, CM, id), \ CM 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_START_CNTL_R, CM, id), \ CM 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_END_CNTL_B, CM, id), \ CM 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_END_CNTL_G, CM, id), \ CM 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_END_CNTL_R, CM, id), \ CM 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_0_1, CM, id), \ CM 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_2_3, CM, id), \ CM 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_4_5, CM, id), \ CM 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_6_7, CM, id), \ CM 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_8_9, CM, id), \ CM 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_10_11, CM, id), \ CM 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_12_13, CM, id), \ CM 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_14_15, CM, id), \ CM 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_16_17, CM, id), \ CM 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_18_19, CM, id), \ CM 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_20_21, CM, id), \ CM 121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_22_23, CM, id), \ CM 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_24_25, CM, id), \ CM 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_26_27, CM, id), \ CM 124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_28_29, CM, id), \ CM 125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_30_31, CM, id), \ CM 126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMB_REGION_32_33, CM, id), \ CM 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_START_CNTL_B, CM, id), \ CM 128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_START_CNTL_G, CM, id), \ CM 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_START_CNTL_R, CM, id), \ CM 130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_END_CNTL_B, CM, id), \ CM 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_END_CNTL_G, CM, id), \ CM 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_END_CNTL_R, CM, id), \ CM 133 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_0_1, CM, id), \ CM 134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_2_3, CM, id), \ CM 135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_4_5, CM, id), \ CM 136 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_6_7, CM, id), \ CM 137 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_8_9, CM, id), \ CM 138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_10_11, CM, id), \ CM 139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_12_13, CM, id), \ CM 140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_14_15, CM, id), \ CM 141 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_16_17, CM, id), \ CM 142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_18_19, CM, id), \ CM 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_20_21, CM, id), \ CM 144 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_22_23, CM, id), \ CM 145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_24_25, CM, id), \ CM 146 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_26_27, CM, id), \ CM 147 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_28_29, CM, id), \ CM 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_30_31, CM, id), \ CM 149 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_RAMA_REGION_32_33, CM, id), \ CM 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_LUT_INDEX, CM, id), \ CM 164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h SRI(CM_SHAPER_LUT_DATA, CM, id), \ CM 314 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c phy_write(phy, CM(priv->cfg.cm), DPHY_CM);