ipic_read 529 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_read 545 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_read 584 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_read 642 arch/powerpc/sysdev/ipic.c vold = ipic_read(ipic->regs, IPIC_SECNR); ipic_read 749 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, IPIC_SEMSR); ipic_read 782 arch/powerpc/sysdev/ipic.c return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0; ipic_read 798 arch/powerpc/sysdev/ipic.c irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK; ipic_read 823 arch/powerpc/sysdev/ipic.c ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR); ipic_read 824 arch/powerpc/sysdev/ipic.c ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A); ipic_read 825 arch/powerpc/sysdev/ipic.c ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D); ipic_read 826 arch/powerpc/sysdev/ipic.c ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H); ipic_read 827 arch/powerpc/sysdev/ipic.c ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L); ipic_read 828 arch/powerpc/sysdev/ipic.c ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR); ipic_read 829 arch/powerpc/sysdev/ipic.c ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A); ipic_read 830 arch/powerpc/sysdev/ipic.c ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B); ipic_read 831 arch/powerpc/sysdev/ipic.c ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR); ipic_read 832 arch/powerpc/sysdev/ipic.c ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR); ipic_read 833 arch/powerpc/sysdev/ipic.c ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR); ipic_read 834 arch/powerpc/sysdev/ipic.c ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);