io_p2v 41 arch/arm/mach-lpc32xx/common.c iramptr1 = io_p2v(LPC32XX_IRAM_BASE); io_p2v 42 arch/arm/mach-lpc32xx/common.c iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE); io_p2v 59 arch/arm/mach-lpc32xx/common.c *mapbase = io_p2v(LPC32XX_IRAM_BASE); io_p2v 121 arch/arm/mach-lpc32xx/lpc32xx.h #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ io_p2v 576 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) io_p2v 577 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) io_p2v 578 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) io_p2v 579 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) io_p2v 580 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) io_p2v 581 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) io_p2v 586 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) io_p2v 587 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) io_p2v 588 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) io_p2v 589 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) io_p2v 590 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) io_p2v 591 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) io_p2v 592 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) io_p2v 593 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) io_p2v 594 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) io_p2v 595 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) io_p2v 596 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) io_p2v 597 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) io_p2v 598 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) io_p2v 599 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) io_p2v 600 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) io_p2v 601 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) io_p2v 602 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) io_p2v 626 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) io_p2v 627 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) io_p2v 628 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) io_p2v 629 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) io_p2v 630 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) io_p2v 631 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) io_p2v 632 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) io_p2v 633 arch/arm/mach-lpc32xx/lpc32xx.h #define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) io_p2v 638 arch/arm/mach-lpc32xx/lpc32xx.h #define _UCREG(x) io_p2v(\ io_p2v 672 arch/arm/mach-lpc32xx/lpc32xx.h #define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) io_p2v 692 arch/arm/mach-lpc32xx/lpc32xx.h #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) io_p2v 124 arch/arm/mach-lpc32xx/pm.c #define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS) io_p2v 54 arch/arm/mach-pxa/generic.c pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); io_p2v 15 arch/arm/mach-pxa/include/mach/dma.h #define DMAC_REGS_VIRT io_p2v(0x40000000) io_p2v 40 arch/arm/mach-pxa/include/mach/hardware.h # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x))) io_p2v 51 arch/arm/mach-pxa/include/mach/hardware.h # define __REG(x) io_p2v(x) io_p2v 19 arch/arm/mach-pxa/include/mach/mtd-xip.h #define ICIP io_p2v(0x40d00000) io_p2v 20 arch/arm/mach-pxa/include/mach/mtd-xip.h #define ICMR io_p2v(0x40d00004) io_p2v 134 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ io_p2v 135 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */ io_p2v 136 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define CKEN io_p2v(0x41300004) /* Clock Enable Register */ io_p2v 137 arch/arm/mach-pxa/include/mach/pxa2xx-regs.h #define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */ io_p2v 18 arch/arm/mach-pxa/include/mach/pxa3xx-regs.h #define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */ io_p2v 11 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSMR0 io_p2v(0x40A00000) /* */ io_p2v 12 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSMR1 io_p2v(0x40A00004) /* */ io_p2v 13 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSMR2 io_p2v(0x40A00008) /* */ io_p2v 14 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSMR3 io_p2v(0x40A0000C) /* */ io_p2v 15 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSMR4 io_p2v(0x40A00080) /* */ io_p2v 16 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */ io_p2v 17 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */ io_p2v 18 arch/arm/mach-pxa/include/mach/regs-ost.h #define OMCR4 io_p2v(0x40A000C0) /* */ io_p2v 19 arch/arm/mach-pxa/include/mach/regs-ost.h #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ io_p2v 20 arch/arm/mach-pxa/include/mach/regs-ost.h #define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */ io_p2v 21 arch/arm/mach-pxa/include/mach/regs-ost.h #define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */ io_p2v 172 arch/arm/mach-pxa/irq.c pxa_irq_base = io_p2v(0x40d00000); io_p2v 257 arch/arm/mach-pxa/irq.c pxa_irq_base = io_p2v(res.start); io_p2v 178 arch/arm/mach-pxa/pxa27x-udc.h #define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) io_p2v 86 arch/arm/mach-pxa/pxa300.c mfp_init_base(io_p2v(MFPR_BASE)); io_p2v 80 arch/arm/mach-pxa/pxa320.c mfp_init_base(io_p2v(MFPR_BASE)); io_p2v 202 arch/arm/mach-pxa/pxa930.c mfp_init_base(io_p2v(MFPR_BASE)); io_p2v 632 arch/arm/mach-sa1100/assabet.c unsigned long virt = (unsigned long)io_p2v(phys); io_p2v 411 arch/arm/mach-sa1100/generic.c pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x90000000)); io_p2v 834 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ io_p2v 835 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ io_p2v 836 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ io_p2v 837 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ io_p2v 838 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ io_p2v 839 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ io_p2v 840 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ io_p2v 841 arch/arm/mach-sa1100/include/mach/SA-1100.h #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ io_p2v 40 arch/arm/mach-sa1100/include/mach/hardware.h #define __MREG(x) IOMEM(io_p2v(x)) io_p2v 44 arch/arm/mach-sa1100/include/mach/hardware.h # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) io_p2v 49 arch/arm/mach-sa1100/include/mach/hardware.h # define __REG(x) io_p2v(x) io_p2v 31 arch/unicore32/include/mach/PKUnity.h #define PKUNITY_PCI_BASE io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */ io_p2v 43 arch/unicore32/include/mach/PKUnity.h #define PKUNITY_AHB_BASE io_p2v(0xC0000000) io_p2v 68 arch/unicore32/include/mach/PKUnity.h #define PKUNITY_APB_BASE io_p2v(0xEE000000)