CLK_TOP_MUX_UART  339 drivers/clk/mediatek/clk-mt6797.c 	MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
CLK_TOP_MUX_UART  570 drivers/clk/mediatek/clk-mt8183.c 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",