in_be64           433 arch/powerpc/include/asm/eeh.h 	u64 val = in_be64(addr);
in_be64           168 arch/powerpc/include/asm/io.h DEF_MMIO_IN_D(in_be64, 64, ld);
in_be64           173 arch/powerpc/include/asm/io.h 	return swab64(in_be64(addr));
in_be64           510 arch/powerpc/include/asm/io.h #define __do_readq_be(addr)	in_be64(PCI_FIX_ADDR(addr))
in_be64            37 arch/powerpc/kvm/book3s_xive_native.c 	val = in_be64(xd->eoi_mmio + offset);
in_be64            83 arch/powerpc/platforms/cell/cbe_thermal.c 	value.val = in_be64(&reg->val);
in_be64           105 arch/powerpc/platforms/cell/cbe_thermal.c 	value = in_be64(&pmd_regs->tm_tpr.val);
in_be64           127 arch/powerpc/platforms/cell/cbe_thermal.c 	reg_value = in_be64(&pmd_regs->tm_tpr.val);
in_be64           180 arch/powerpc/platforms/cell/cbe_thermal.c 	value = in_be64(&pmd_regs->ts_ctsr2);
in_be64           100 arch/powerpc/platforms/cell/interrupt.c 		bits = in_be64(&node_iic->iic_is);
in_be64           141 arch/powerpc/platforms/cell/interrupt.c 		in_be64((u64 __iomem *) &iic->regs->pending_destr);
in_be64           146 arch/powerpc/platforms/cell/iommu.c 		while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
in_be64           235 arch/powerpc/platforms/cell/iommu.c 	stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
in_be64           393 arch/powerpc/platforms/cell/iommu.c 	reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
in_be64           409 arch/powerpc/platforms/cell/iommu.c 	in_be64(iommu->xlate_regs + IOC_IOST_Origin);
in_be64           412 arch/powerpc/platforms/cell/iommu.c 	reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
in_be64           699 arch/powerpc/platforms/cell/iommu.c 		(void)in_be64(xregs + IOC_IOST_Origin);
in_be64           700 arch/powerpc/platforms/cell/iommu.c 		val = in_be64(cregs + IOC_IOCmd_Cfg);
in_be64           703 arch/powerpc/platforms/cell/iommu.c 		(void)in_be64(cregs + IOC_IOCmd_Cfg);
in_be64           118 arch/powerpc/platforms/cell/pervasive.c 		out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
in_be64            53 arch/powerpc/platforms/cell/pmu.c 		(val) = (u32)(in_be64(&pmd_regs->reg) >> 32);	\
in_be64           327 arch/powerpc/platforms/cell/pmu.c 	*buf++ = in_be64(&pmd_regs->trace_buffer_0_63);
in_be64           328 arch/powerpc/platforms/cell/pmu.c 	*buf++ = in_be64(&pmd_regs->trace_buffer_64_127);
in_be64            39 arch/powerpc/platforms/cell/ras.c 	       in_be64(&pregs->checkstop_fir));
in_be64            41 arch/powerpc/platforms/cell/ras.c 	       in_be64(&pregs->checkstop_fir));
in_be64            43 arch/powerpc/platforms/cell/ras.c 	       in_be64(&pregs->spec_att_mchk_fir));
in_be64            48 arch/powerpc/platforms/cell/ras.c 	       in_be64(&iregs->ioc_fir));
in_be64           288 arch/powerpc/platforms/cell/ras.c 		if (in_be64(&regs->ras_esc_0) & 0x0000ffff) {
in_be64            31 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
in_be64            39 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
in_be64            50 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->int_mask_RW[class]);
in_be64            60 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->int_stat_RW[class]);
in_be64            83 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_dar_RW);
in_be64            88 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_dsisr_RW);
in_be64           108 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_sr1_RW);
in_be64           118 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_tclass_id_RW);
in_be64           133 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->resource_allocation_groupID_RW);
in_be64           143 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->resource_allocation_enable_RW);
in_be64          2515 arch/powerpc/platforms/cell/spufs/file.c 		mfc_control_RW = in_be64(&priv2->mfc_control_RW);
in_be64            92 arch/powerpc/platforms/cell/spufs/hw_ops.c 		*data = in_be64(&priv2->puint_mb_R);
in_be64           141 arch/powerpc/platforms/cell/spufs/hw_ops.c 	tmp = in_be64(&priv2->spu_cfg_RW);
in_be64           152 arch/powerpc/platforms/cell/spufs/hw_ops.c 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
in_be64           162 arch/powerpc/platforms/cell/spufs/hw_ops.c 	tmp = in_be64(&priv2->spu_cfg_RW);
in_be64           173 arch/powerpc/platforms/cell/spufs/hw_ops.c 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
in_be64           110 arch/powerpc/platforms/cell/spufs/run.c 	while ((in_be64(mfc_cntl) & MFC_CNTL_PURGE_DMA_STATUS_MASK)
in_be64           174 arch/powerpc/platforms/cell/spufs/switch.c 	switch (in_be64(&priv2->mfc_control_RW) &
in_be64           177 arch/powerpc/platforms/cell/spufs/switch.c 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
in_be64           184 arch/powerpc/platforms/cell/spufs/switch.c 				in_be64(&priv2->mfc_control_RW) |
in_be64           189 arch/powerpc/platforms/cell/spufs/switch.c 		POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
in_be64           194 arch/powerpc/platforms/cell/spufs/switch.c 				in_be64(&priv2->mfc_control_RW) &
in_be64           260 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
in_be64           304 arch/powerpc/platforms/cell/spufs/switch.c 	POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
in_be64           342 arch/powerpc/platforms/cell/spufs/switch.c 	if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
in_be64           345 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->puq[i].mfc_cq_data0_RW);
in_be64           347 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->puq[i].mfc_cq_data1_RW);
in_be64           349 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->puq[i].mfc_cq_data2_RW);
in_be64           351 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->puq[i].mfc_cq_data3_RW);
in_be64           355 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
in_be64           357 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
in_be64           359 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
in_be64           361 arch/powerpc/platforms/cell/spufs/switch.c 			    in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
in_be64           410 arch/powerpc/platforms/cell/spufs/switch.c 	    in_be64(&priv2->spu_tag_status_query_RW);
in_be64           421 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
in_be64           422 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
in_be64           433 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
in_be64           478 arch/powerpc/platforms/cell/spufs/switch.c 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
in_be64           518 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
in_be64           540 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
in_be64           562 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
in_be64           612 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
in_be64           626 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
in_be64           633 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
in_be64           634 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
in_be64           651 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
in_be64           653 arch/powerpc/platforms/cell/spufs/switch.c 		csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
in_be64           668 arch/powerpc/platforms/cell/spufs/switch.c 	csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
in_be64           984 arch/powerpc/platforms/cell/spufs/switch.c 	POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
in_be64          1682 arch/powerpc/platforms/cell/spufs/switch.c 		dummy = in_be64(&priv2->puint_mb_R);
in_be64           174 arch/powerpc/platforms/powernv/eeh-powernv.c 	*val = in_be64(phb->regs + offset);
in_be64           109 arch/powerpc/platforms/powernv/rng.c 	*v = rng_whiten(rng, in_be64(rng->regs));
in_be64           157 arch/powerpc/platforms/powernv/rng.c 	val = in_be64(rng->regs);
in_be64           444 arch/powerpc/platforms/powernv/vas.h 	return in_be64(win->hvwc_map+reg);
in_be64           368 arch/powerpc/platforms/ps3/spu.c 	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
in_be64           514 arch/powerpc/platforms/ps3/spu.c 	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
in_be64           524 arch/powerpc/platforms/ps3/spu.c 	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
in_be64           206 arch/powerpc/sysdev/xive/common.c 		val = in_be64(xd->eoi_mmio + offset);
in_be64           406 arch/powerpc/sysdev/xive/native.c 		in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
in_be64           443 arch/powerpc/sysdev/xive/native.c 	in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
in_be64            65 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	value = in_be64(&pmd_regs->pmcr);
in_be64            75 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	value = in_be64(&pmd_regs->pmsr) & 0x07;
in_be64            78 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 		value = in_be64(&pmd_regs->pmsr) & 0x07;
in_be64            98 drivers/cpufreq/ppc_cbe_cpufreq_pervasive.c 	ret = in_be64(&pmd_regs->pmsr) & 0x07;
in_be64           202 drivers/dma/fsldma.h #define fsl_ioread64be(p)	in_be64(p)
in_be64            84 drivers/edac/cell_edac.c 	fir = in_be64(&priv->regs->mic_fir);
in_be64            92 drivers/edac/cell_edac.c 		addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
in_be64            97 drivers/edac/cell_edac.c 		addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
in_be64           102 drivers/edac/cell_edac.c 		addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
in_be64           107 drivers/edac/cell_edac.c 		addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
in_be64           118 drivers/edac/cell_edac.c 		(void)in_be64(&priv->regs->mic_fir);
in_be64           122 drivers/edac/cell_edac.c 		fir = in_be64(&priv->regs->mic_fir);
in_be64           184 drivers/edac/cell_edac.c 	reg = in_be64(&regs->mic_mnt_cfg);
in_be64           197 drivers/edac/cell_edac.c 		in_be64(&regs->mic_fir));
in_be64           789 drivers/misc/cxl/cxl.h 		return in_be64(_cxl_p1_addr(cxl, reg));
in_be64           809 drivers/misc/cxl/cxl.h 		return in_be64(_cxl_p1n_addr(afu, reg));
in_be64           828 drivers/misc/cxl/cxl.h 		return in_be64(_cxl_p2n_addr(afu, reg));
in_be64            17 drivers/misc/cxl/debugfs.c 	*val = in_be64((u64 __iomem *)data);
in_be64            89 drivers/misc/cxl/pci.c #define AFUD_READ(afu, off)		in_be64(afu->native->afu_desc_mmio + off)
in_be64           103 drivers/misc/ocxl/link.c 	*dsisr = in_be64(spa->reg_dsisr);
in_be64           104 drivers/misc/ocxl/link.c 	*dar = in_be64(spa->reg_dar);
in_be64           105 drivers/misc/ocxl/link.c 	reg = in_be64(spa->reg_pe_handle);
in_be64           814 sound/ppc/snd_ps3.c 	the_card.audio_irq_outlet = in_be64(mapped);