imx_writew        116 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(reg, brd_io + INTR_MASK_REG);
imx_writew        123 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(1 << expio, brd_io + INTR_RESET_REG);
imx_writew        124 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(0, brd_io + INTR_RESET_REG);
imx_writew        135 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(reg, brd_io + INTR_MASK_REG);
imx_writew        178 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(0, brd_io + INTR_MASK_REG);
imx_writew        179 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(0xFFFF, brd_io + INTR_RESET_REG);
imx_writew        180 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(0, brd_io + INTR_RESET_REG);
imx_writew        181 arch/arm/mach-imx/3ds_debugboard.c 	imx_writew(0x1F, brd_io + INTR_MASK_REG);
imx_writew        199 arch/arm/mach-imx/mach-mx27ads.c 		imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
imx_writew        201 arch/arm/mach-imx/mach-mx27ads.c 		imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
imx_writew        174 arch/arm/mach-imx/mach-mx31ads.c 	imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
imx_writew        186 arch/arm/mach-imx/mach-mx31ads.c 	imx_writew(1 << expio, PBC_INTSTATUS_REG);
imx_writew        197 arch/arm/mach-imx/mach-mx31ads.c 	imx_writew(1 << expio, PBC_INTMASK_SET_REG);
imx_writew        220 arch/arm/mach-imx/mach-mx31ads.c 	imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
imx_writew        221 arch/arm/mach-imx/mach-mx31ads.c 	imx_writew(0xFFFF, PBC_INTSTATUS_REG);
imx_writew        491 arch/arm/mach-imx/mach-mx31moboard.c 	imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
imx_writew         42 arch/arm/mach-imx/system.c 	imx_writew(wcr_enable, wdog_base);
imx_writew         50 arch/arm/mach-imx/system.c 	imx_writew(wcr_enable, wdog_base);
imx_writew         51 arch/arm/mach-imx/system.c 	imx_writew(wcr_enable, wdog_base);