imx_writel 60 arch/arm/mach-imx/avic.c imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); imx_writel 64 arch/arm/mach-imx/avic.c imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); imx_writel 88 arch/arm/mach-imx/avic.c imx_writel(gc->wake_active, avic_base + ct->regs.mask); imx_writel 99 arch/arm/mach-imx/avic.c imx_writel(~gc->wake_active, mx25_ccm_base + offs); imx_writel 109 arch/arm/mach-imx/avic.c imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); imx_writel 115 arch/arm/mach-imx/avic.c imx_writel(0xffffffff, mx25_ccm_base + offs); imx_writel 181 arch/arm/mach-imx/avic.c imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); imx_writel 182 arch/arm/mach-imx/avic.c imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); imx_writel 188 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_INTCNTL); imx_writel 189 arch/arm/mach-imx/avic.c imx_writel(0x1f, avic_base + AVIC_NIMASK); imx_writel 192 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_INTENABLEH); imx_writel 193 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_INTENABLEL); imx_writel 196 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_INTTYPEH); imx_writel 197 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_INTTYPEL); imx_writel 212 arch/arm/mach-imx/avic.c imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); imx_writel 47 arch/arm/mach-imx/cpu.c imx_writel(0x77777777, base + 0x0); imx_writel 48 arch/arm/mach-imx/cpu.c imx_writel(0x77777777, base + 0x4); imx_writel 55 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x40); imx_writel 56 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x44); imx_writel 57 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x48); imx_writel 58 arch/arm/mach-imx/cpu.c imx_writel(0x0, base + 0x4C); imx_writel 60 arch/arm/mach-imx/cpu.c imx_writel(reg, base + 0x50); imx_writel 50 arch/arm/mach-imx/iomux-imx31.c imx_writel(l, reg); imx_writel 75 arch/arm/mach-imx/iomux-imx31.c imx_writel(l, reg); imx_writel 159 arch/arm/mach-imx/iomux-imx31.c imx_writel(l, IOMUXGPR); imx_writel 33 arch/arm/mach-imx/iomux-v1.c imx_writel(val, imx_iomuxv1_baseaddr + offset); imx_writel 35 arch/arm/mach-imx/iomux-v3.c imx_writel(mux_mode, base + mux_ctrl_ofs); imx_writel 38 arch/arm/mach-imx/iomux-v3.c imx_writel(sel_input, base + sel_input_ofs); imx_writel 41 arch/arm/mach-imx/iomux-v3.c imx_writel(pad_ctrl, base + pad_ctrl_ofs); imx_writel 502 arch/arm/mach-imx/mach-armadillo5x0.c imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30), imx_writel 38 arch/arm/mach-imx/mach-imx51.c imx_writel(0xf00, hsc_addr); imx_writel 41 arch/arm/mach-imx/mach-imx51.c imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); imx_writel 183 arch/arm/mach-imx/mach-qong.c imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); imx_writel 184 arch/arm/mach-imx/mach-qong.c imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); imx_writel 185 arch/arm/mach-imx/mach-qong.c imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); imx_writel 132 arch/arm/mach-imx/mm-imx3.c imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); imx_writel 225 arch/arm/mach-imx/mm-imx3.c imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); imx_writel 24 arch/arm/mach-imx/pm-imx27.c imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); imx_writel 193 arch/arm/mach-imx/pm-imx5.c imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); imx_writel 194 arch/arm/mach-imx/pm-imx5.c imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); imx_writel 195 arch/arm/mach-imx/pm-imx5.c imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); imx_writel 196 arch/arm/mach-imx/pm-imx5.c imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); imx_writel 202 arch/arm/mach-imx/pm-imx5.c imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); imx_writel 203 arch/arm/mach-imx/pm-imx5.c imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); imx_writel 225 arch/arm/mach-imx/pm-imx5.c imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); imx_writel 226 arch/arm/mach-imx/pm-imx5.c imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); imx_writel 64 arch/arm/mach-imx/tzic.c imx_writel(value, tzic_base + TZIC_INTSEC0(index)); imx_writel 78 arch/arm/mach-imx/tzic.c imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); imx_writel 85 arch/arm/mach-imx/tzic.c imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), imx_writel 162 arch/arm/mach-imx/tzic.c imx_writel(0x80010001, tzic_base + TZIC_INTCNTL); imx_writel 163 arch/arm/mach-imx/tzic.c imx_writel(0x1f, tzic_base + TZIC_PRIOMASK); imx_writel 164 arch/arm/mach-imx/tzic.c imx_writel(0x02, tzic_base + TZIC_SYNCCTRL); imx_writel 167 arch/arm/mach-imx/tzic.c imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); imx_writel 171 arch/arm/mach-imx/tzic.c imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); imx_writel 211 arch/arm/mach-imx/tzic.c imx_writel(1, tzic_base + TZIC_DSMINT); imx_writel 216 arch/arm/mach-imx/tzic.c imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),