imx_clk_divider_gate  116 drivers/clk/imx/clk-imx7ulp.c 	clks[IMX7ULP_CLK_SPLL_BUS_CLK]	= imx_clk_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);
imx_clk_divider_gate  127 drivers/clk/imx/clk-imx7ulp.c 	clks[IMX7ULP_CLK_DDR_DIV]	= imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
imx_clk_divider_gate  136 drivers/clk/imx/clk-imx7ulp.c 	clks[IMX7ULP_CLK_SOSC_BUS_CLK]	= imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
imx_clk_divider_gate  138 drivers/clk/imx/clk-imx7ulp.c 	clks[IMX7ULP_CLK_FIRC_BUS_CLK]	= imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
imx_clk_divider_gate  469 drivers/clk/imx/clk.h struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,