igcsr32            38 arch/alpha/include/asm/core_irongate.h 	igcsr32 dev_vendor;		/* 0x00 - device ID, vendor ID */
igcsr32            39 arch/alpha/include/asm/core_irongate.h 	igcsr32 stat_cmd;		/* 0x04 - status, command */
igcsr32            40 arch/alpha/include/asm/core_irongate.h 	igcsr32 class;			/* 0x08 - class code, rev ID */
igcsr32            41 arch/alpha/include/asm/core_irongate.h 	igcsr32 latency;		/* 0x0C - header type, PCI latency */
igcsr32            42 arch/alpha/include/asm/core_irongate.h 	igcsr32 bar0;			/* 0x10 - BAR0 - AGP */
igcsr32            43 arch/alpha/include/asm/core_irongate.h 	igcsr32 bar1;			/* 0x14 - BAR1 - GART */
igcsr32            44 arch/alpha/include/asm/core_irongate.h 	igcsr32 bar2;			/* 0x18 - Power Management reg block */
igcsr32            46 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd0[6];		/* 0x1C-0x33 reserved */
igcsr32            48 arch/alpha/include/asm/core_irongate.h 	igcsr32 capptr;			/* 0x34 - Capabilities pointer */
igcsr32            50 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd1[2];		/* 0x38-0x3F reserved */
igcsr32            52 arch/alpha/include/asm/core_irongate.h 	igcsr32 bacsr10;		/* 0x40 - base address chip selects */
igcsr32            53 arch/alpha/include/asm/core_irongate.h 	igcsr32 bacsr32;		/* 0x44 - base address chip selects */
igcsr32            54 arch/alpha/include/asm/core_irongate.h 	igcsr32 bacsr54_eccms761;	/* 0x48 - 751: base addr. chip selects
igcsr32            57 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd2[1];		/* 0x4C-0x4F reserved */
igcsr32            59 arch/alpha/include/asm/core_irongate.h 	igcsr32 drammap;		/* 0x50 - address mapping control */
igcsr32            60 arch/alpha/include/asm/core_irongate.h 	igcsr32 dramtm;			/* 0x54 - timing, driver strength */
igcsr32            61 arch/alpha/include/asm/core_irongate.h 	igcsr32 dramms;			/* 0x58 - DRAM mode/status */
igcsr32            63 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd3[1];		/* 0x5C-0x5F reserved */
igcsr32            65 arch/alpha/include/asm/core_irongate.h 	igcsr32 biu0;			/* 0x60 - bus interface unit */
igcsr32            66 arch/alpha/include/asm/core_irongate.h 	igcsr32 biusip;			/* 0x64 - Serial initialisation pkt */
igcsr32            68 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd4[2];		/* 0x68-0x6F reserved */
igcsr32            70 arch/alpha/include/asm/core_irongate.h 	igcsr32 mro;			/* 0x70 - memory request optimiser */
igcsr32            72 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd5[3];		/* 0x74-0x7F reserved */
igcsr32            74 arch/alpha/include/asm/core_irongate.h 	igcsr32 whami;			/* 0x80 - who am I */
igcsr32            75 arch/alpha/include/asm/core_irongate.h 	igcsr32 pciarb;			/* 0x84 - PCI arbitration control */
igcsr32            76 arch/alpha/include/asm/core_irongate.h 	igcsr32 pcicfg;			/* 0x88 - PCI config status */
igcsr32            78 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd6[4];		/* 0x8C-0x9B reserved */
igcsr32            80 arch/alpha/include/asm/core_irongate.h 	igcsr32 pci_mem;		/* 0x9C - PCI top of memory,
igcsr32            84 arch/alpha/include/asm/core_irongate.h 	igcsr32 agpcap;			/* 0xA0 - AGP Capability Identifier */
igcsr32            85 arch/alpha/include/asm/core_irongate.h 	igcsr32 agpstat;		/* 0xA4 - AGP status register */
igcsr32            86 arch/alpha/include/asm/core_irongate.h 	igcsr32 agpcmd;			/* 0xA8 - AGP control register */
igcsr32            87 arch/alpha/include/asm/core_irongate.h 	igcsr32 agpva;			/* 0xAC - AGP Virtual Address Space */
igcsr32            88 arch/alpha/include/asm/core_irongate.h 	igcsr32 agpmode;		/* 0xB0 - AGP/GART mode control */
igcsr32            94 arch/alpha/include/asm/core_irongate.h 	igcsr32 dev_vendor;		/* 0x00 - Device and Vendor IDs */
igcsr32            95 arch/alpha/include/asm/core_irongate.h 	igcsr32 stat_cmd;		/* 0x04 - Status and Command regs */
igcsr32            96 arch/alpha/include/asm/core_irongate.h 	igcsr32 class;			/* 0x08 - subclass, baseclass etc */
igcsr32            97 arch/alpha/include/asm/core_irongate.h 	igcsr32 htype;			/* 0x0C - header type (at 0x0E) */
igcsr32            98 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd0[2];		/* 0x10-0x17 reserved */
igcsr32            99 arch/alpha/include/asm/core_irongate.h 	igcsr32 busnos;			/* 0x18 - Primary, secondary bus nos */
igcsr32           100 arch/alpha/include/asm/core_irongate.h 	igcsr32 io_baselim_regs;	/* 0x1C - IO base, IO lim, AGP status */
igcsr32           101 arch/alpha/include/asm/core_irongate.h 	igcsr32	mem_baselim;		/* 0x20 - memory base, memory lim */
igcsr32           102 arch/alpha/include/asm/core_irongate.h 	igcsr32 pfmem_baselim;		/* 0x24 - prefetchable base, lim */
igcsr32           103 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd1[2];		/* 0x28-0x2F reserved */
igcsr32           104 arch/alpha/include/asm/core_irongate.h 	igcsr32 io_baselim;		/* 0x30 - IO base, IO limit */
igcsr32           105 arch/alpha/include/asm/core_irongate.h 	igcsr32 rsrvd2[2];		/* 0x34-0x3B - reserved */
igcsr32           106 arch/alpha/include/asm/core_irongate.h 	igcsr32 interrupt;		/* 0x3C - interrupt, PCI bridge ctrl */
igcsr32           110 arch/alpha/include/asm/core_irongate.h extern igcsr32 *IronECC;
igcsr32            44 arch/alpha/kernel/core_irongate.c igcsr32 *IronECC;