idma_mask         333 drivers/gpu/ipu-v3/ipu-common.c 	ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
idma_mask         347 drivers/gpu/ipu-v3/ipu-common.c 		reg |= idma_mask(channel->num);
idma_mask         349 drivers/gpu/ipu-v3/ipu-common.c 		reg &= ~idma_mask(channel->num);
idma_mask         492 drivers/gpu/ipu-v3/ipu-common.c 	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
idma_mask         516 drivers/gpu/ipu-v3/ipu-common.c 	return ((reg & idma_mask(channel->num)) != 0);
idma_mask         530 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
idma_mask         532 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
idma_mask         549 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
idma_mask         552 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
idma_mask         555 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
idma_mask         575 drivers/gpu/ipu-v3/ipu-common.c 	val |= idma_mask(channel->num);
idma_mask         586 drivers/gpu/ipu-v3/ipu-common.c 	return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
idma_mask         597 drivers/gpu/ipu-v3/ipu-common.c 			idma_mask(channel->num)) {
idma_mask         617 drivers/gpu/ipu-v3/ipu-common.c 	val &= ~idma_mask(channel->num);
idma_mask         626 drivers/gpu/ipu-v3/ipu-common.c 			idma_mask(channel->num)) {
idma_mask         627 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(channel->num),
idma_mask         632 drivers/gpu/ipu-v3/ipu-common.c 			idma_mask(channel->num)) {
idma_mask         633 drivers/gpu/ipu-v3/ipu-common.c 		ipu_cm_write(ipu, idma_mask(channel->num),
idma_mask         641 drivers/gpu/ipu-v3/ipu-common.c 	val &= ~idma_mask(channel->num);