i915_reg_t 284 drivers/gpu/drm/i915/display/intel_audio.c i915_reg_t reg_eldv, u32 bits_eldv, i915_reg_t 285 drivers/gpu/drm/i915/display/intel_audio.c i915_reg_t reg_elda, u32 bits_elda, i915_reg_t 286 drivers/gpu/drm/i915/display/intel_audio.c i915_reg_t reg_edid) i915_reg_t 561 drivers/gpu/drm/i915/display/intel_audio.c i915_reg_t aud_config, aud_cntrl_st2; i915_reg_t 610 drivers/gpu/drm/i915/display/intel_audio.c i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; i915_reg_t 94 drivers/gpu/drm/i915/display/intel_combo_phy.c enum phy phy, i915_reg_t reg, u32 mask, i915_reg_t 60 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg; i915_reg_t 74 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg, enum pipe *pipe) i915_reg_t 650 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t bclrpat_reg, vtotal_reg, i915_reg_t 954 drivers/gpu/drm/i915/display/intel_crt.c i915_reg_t adpa_reg; i915_reg_t 17 drivers/gpu/drm/i915/display/intel_crt.h i915_reg_t adpa_reg, enum pipe *pipe); i915_reg_t 987 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = DDI_BUF_CTL(port); i915_reg_t 1229 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg) i915_reg_t 1856 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); i915_reg_t 3489 drivers/gpu/drm/i915/display/intel_ddi.c static i915_reg_t i915_reg_t 3493 drivers/gpu/drm/i915/display/intel_ddi.c static const i915_reg_t regs[] = { i915_reg_t 3532 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); i915_reg_t 1032 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPEDSL(pipe); i915_reg_t 1077 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPECONF(cpu_transcoder); i915_reg_t 1187 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t pp_reg; i915_reg_t 1316 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t dp_reg) i915_reg_t 1334 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t hdmi_reg) i915_reg_t 1487 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = DPLL(crtc->pipe); i915_reg_t 1593 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t dpll_reg; i915_reg_t 1625 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 1709 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 1799 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 1857 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4441 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4484 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4585 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4718 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4836 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4873 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 4904 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 5271 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = TRANS_DP_CTL(pipe); i915_reg_t 5316 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t dslreg = PIPEDSL(pipe); i915_reg_t 6599 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; i915_reg_t 15933 drivers/gpu/drm/i915/display/intel_display.c static i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) i915_reg_t 15948 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); i915_reg_t 16444 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPECONF(cpu_transcoder); i915_reg_t 16596 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); i915_reg_t 16882 drivers/gpu/drm/i915/display/intel_display.c enum port port, i915_reg_t hdmi_reg) i915_reg_t 16900 drivers/gpu/drm/i915/display/intel_display.c enum port port, i915_reg_t dp_reg) i915_reg_t 4109 drivers/gpu/drm/i915/display/intel_display_power.c i915_reg_t reg, bool enable) i915_reg_t 4468 drivers/gpu/drm/i915/display/intel_display_power.c i915_reg_t reg; i915_reg_t 153 drivers/gpu/drm/i915/display/intel_display_power.h i915_reg_t bios; i915_reg_t 154 drivers/gpu/drm/i915/display/intel_display_power.h i915_reg_t driver; i915_reg_t 155 drivers/gpu/drm/i915/display/intel_display_power.h i915_reg_t kvmr; i915_reg_t 156 drivers/gpu/drm/i915/display/intel_display_power.h i915_reg_t debug; i915_reg_t 1097 drivers/gpu/drm/i915/display/intel_display_types.h i915_reg_t hdmi_reg; i915_reg_t 1148 drivers/gpu/drm/i915/display/intel_display_types.h i915_reg_t output_reg; i915_reg_t 1230 drivers/gpu/drm/i915/display/intel_display_types.h i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); i915_reg_t 1231 drivers/gpu/drm/i915/display/intel_display_types.h i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); i915_reg_t 1014 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl; i915_reg_t 1015 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_stat; i915_reg_t 1016 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_on; i915_reg_t 1017 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_off; i915_reg_t 1018 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_div; i915_reg_t 1046 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t i915_reg_t 1056 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t i915_reg_t 1082 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl_reg, pp_div_reg; i915_reg_t 1146 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); i915_reg_t 1293 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t ch_ctl, ch_data[5]; i915_reg_t 1554 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) i915_reg_t 1571 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) i915_reg_t 1588 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) i915_reg_t 1607 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) i915_reg_t 1626 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) i915_reg_t 1646 drivers/gpu/drm/i915/display/intel_dp.c static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) i915_reg_t 2455 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_stat_reg, pp_ctrl_reg; i915_reg_t 2553 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_stat_reg, pp_ctrl_reg; i915_reg_t 2626 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_stat_reg, pp_ctrl_reg; i915_reg_t 2713 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl_reg; i915_reg_t 2773 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl_reg; i915_reg_t 2832 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); i915_reg_t 2868 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); i915_reg_t 3098 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t dp_reg, enum port port, i915_reg_t 3490 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); i915_reg_t 6704 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); i915_reg_t 7256 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t output_reg, i915_reg_t 39 drivers/gpu/drm/i915/display/intel_dp.h i915_reg_t dp_reg, enum port port, i915_reg_t 41 drivers/gpu/drm/i915/display/intel_dp.h bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, i915_reg_t 492 drivers/gpu/drm/i915/display/intel_dpio_phy.c i915_reg_t reg, u32 mask, u32 expected, i915_reg_t 954 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t ctl, cfgcr1, cfgcr2; i915_reg_t 3107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg) i915_reg_t 3146 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); i915_reg_t 3168 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t cfgcr0_reg, cfgcr1_reg; i915_reg_t 3240 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg) i915_reg_t 3258 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg) i915_reg_t 3274 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); i915_reg_t 3325 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = i915_reg_t 3345 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg) i915_reg_t 3382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); i915_reg_t 3406 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = i915_reg_t 192 drivers/gpu/drm/i915/display/intel_dvo.c i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; i915_reg_t 206 drivers/gpu/drm/i915/display/intel_dvo.c i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; i915_reg_t 285 drivers/gpu/drm/i915/display/intel_dvo.c i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; i915_reg_t 286 drivers/gpu/drm/i915/display/intel_dvo.c i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; i915_reg_t 399 drivers/gpu/drm/i915/display/intel_dvo.c static enum port intel_dvo_port(i915_reg_t dvo_reg) i915_reg_t 36 drivers/gpu/drm/i915/display/intel_dvo_dev.h i915_reg_t dvo_reg; i915_reg_t 37 drivers/gpu/drm/i915/display/intel_dvo_dev.h i915_reg_t dvo_srcdim_reg; i915_reg_t 93 drivers/gpu/drm/i915/display/intel_fifo_underrun.c i915_reg_t reg = PIPESTAT(crtc->pipe); i915_reg_t 114 drivers/gpu/drm/i915/display/intel_fifo_underrun.c i915_reg_t reg = PIPESTAT(pipe); i915_reg_t 165 drivers/gpu/drm/i915/display/intel_hdmi.c static i915_reg_t i915_reg_t 283 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 338 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(pipe); i915_reg_t 360 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 436 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 512 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); i915_reg_t 843 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VIDEO_DIP_CTL; i915_reg_t 952 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg; i915_reg_t 977 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg; i915_reg_t 1026 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 1084 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 1133 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); i915_reg_t 1189 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); i915_reg_t 3161 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t hdmi_reg, enum port port) i915_reg_t 27 drivers/gpu/drm/i915/display/intel_hdmi.h void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, i915_reg_t 69 drivers/gpu/drm/i915/display/intel_lvds.c i915_reg_t reg; i915_reg_t 84 drivers/gpu/drm/i915/display/intel_lvds.c i915_reg_t lvds_reg, enum pipe *pipe) i915_reg_t 823 drivers/gpu/drm/i915/display/intel_lvds.c i915_reg_t lvds_reg; i915_reg_t 17 drivers/gpu/drm/i915/display/intel_lvds.h i915_reg_t lvds_reg, enum pipe *pipe); i915_reg_t 666 drivers/gpu/drm/i915/display/intel_psr.c static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv, i915_reg_t 669 drivers/gpu/drm/i915/display/intel_psr.c static const i915_reg_t regs[] = { i915_reg_t 700 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, i915_reg_t 806 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t psr_status; i915_reg_t 974 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t reg; i915_reg_t 87 drivers/gpu/drm/i915/display/intel_sdvo.c i915_reg_t sdvo_reg; i915_reg_t 1563 drivers/gpu/drm/i915/display/intel_sdvo.c i915_reg_t sdvo_reg, enum pipe *pipe) i915_reg_t 3239 drivers/gpu/drm/i915/display/intel_sdvo.c i915_reg_t sdvo_reg, enum port port) i915_reg_t 19 drivers/gpu/drm/i915/display/intel_sdvo.h i915_reg_t sdvo_reg, enum pipe *pipe); i915_reg_t 21 drivers/gpu/drm/i915/display/intel_sdvo.h i915_reg_t reg, enum port port); i915_reg_t 908 drivers/gpu/drm/i915/display/intel_vdsc.c i915_reg_t dss_ctl1_reg, dss_ctl2_reg; i915_reg_t 944 drivers/gpu/drm/i915/display/intel_vdsc.c i915_reg_t dss_ctl1_reg, dss_ctl2_reg; i915_reg_t 93 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t reg, i915_reg_t 109 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t reg, i915_reg_t 132 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t data_reg, ctrl_reg; i915_reg_t 588 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? i915_reg_t 651 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? i915_reg_t 688 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? i915_reg_t 981 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? i915_reg_t 858 drivers/gpu/drm/i915/gt/intel_engine_cs.c const i915_reg_t mode = RING_MI_MODE(base); i915_reg_t 903 drivers/gpu/drm/i915/gt/intel_engine_cs.c i915_reg_t reg) i915_reg_t 32 drivers/gpu/drm/i915/gt/intel_gt.c static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) i915_reg_t 37 drivers/gpu/drm/i915/gt/intel_gt.c static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) i915_reg_t 42 drivers/gpu/drm/i915/gt/intel_gt.c static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) i915_reg_t 123 drivers/gpu/drm/i915/gt/intel_gt.c i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; i915_reg_t 18 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg; i915_reg_t 65 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; i915_reg_t 79 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg; i915_reg_t 2088 drivers/gpu/drm/i915/gt/intel_lrc.c i915_reg_t reg; i915_reg_t 326 drivers/gpu/drm/i915/gt/intel_mocs.c static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index) i915_reg_t 30 drivers/gpu/drm/i915/gt/intel_reset.c static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set) i915_reg_t 35 drivers/gpu/drm/i915/gt/intel_reset.c static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) i915_reg_t 314 drivers/gpu/drm/i915/gt/intel_reset.c i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; i915_reg_t 316 drivers/gpu/drm/i915/gt/intel_reset.c i915_reg_t sfc_usage; i915_reg_t 381 drivers/gpu/drm/i915/gt/intel_reset.c i915_reg_t sfc_forced_lock; i915_reg_t 447 drivers/gpu/drm/i915/gt/intel_reset.c const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); i915_reg_t 534 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i915_reg_t hwsp; i915_reg_t 1665 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i915_reg_t last_reg = {}; /* keep gcc quiet */ i915_reg_t 149 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, i915_reg_t 163 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) i915_reg_t 169 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val) i915_reg_t 175 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val) i915_reg_t 1034 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) i915_reg_t 1051 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) i915_reg_t 15 drivers/gpu/drm/i915/gt/intel_workarounds_types.h i915_reg_t reg; i915_reg_t 158 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg = i < engine->whitelist.count ? i915_reg_t 869 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg; i915_reg_t 874 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg, i915_reg_t 890 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg) i915_reg_t 902 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 a, u32 b, i915_reg_t reg) i915_reg_t 913 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg) i915_reg_t 924 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 a, u32 b, i915_reg_t reg) i915_reg_t 941 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg)) i915_reg_t 26 drivers/gpu/drm/i915/gt/uc/intel_guc.c static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i) i915_reg_t 21 drivers/gpu/drm/i915/gt/uc/intel_huc.h i915_reg_t reg; i915_reg_t 133 drivers/gpu/drm/i915/gvt/aperture_gm.c i915_reg_t fence_reg_lo, fence_reg_hi; i915_reg_t 1196 drivers/gpu/drm/i915/gvt/cmd_parser.c i915_reg_t stride_reg; i915_reg_t 1197 drivers/gpu/drm/i915/gvt/cmd_parser.c i915_reg_t ctrl_reg; i915_reg_t 1198 drivers/gpu/drm/i915/gvt/cmd_parser.c i915_reg_t surf_reg; i915_reg_t 250 drivers/gpu/drm/i915/gvt/gvt.h i915_reg_t offset; i915_reg_t 460 drivers/gpu/drm/i915/gvt/handlers.c static i915_reg_t force_nonpriv_white_list[] = { i915_reg_t 493 drivers/gpu/drm/i915/gvt/handlers.c i915_reg_t *array = force_nonpriv_white_list; i915_reg_t 581 drivers/gpu/drm/i915/gvt/handlers.c i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; i915_reg_t 622 drivers/gpu/drm/i915/gvt/handlers.c unsigned int next, unsigned int end, i915_reg_t i915_end) i915_reg_t 646 drivers/gpu/drm/i915/gvt/handlers.c i915_reg_t fdi_rx_iir; i915_reg_t 690 drivers/gpu/drm/i915/gvt/handlers.c i915_reg_t status_reg; i915_reg_t 175 drivers/gpu/drm/i915/gvt/interrupt.h i915_reg_t reg_base; i915_reg_t 162 drivers/gpu/drm/i915/gvt/mmio_context.c i915_reg_t offset; i915_reg_t 354 drivers/gpu/drm/i915/gvt/mmio_context.c i915_reg_t reg; i915_reg_t 395 drivers/gpu/drm/i915/gvt/mmio_context.c i915_reg_t offset, l3_offset; i915_reg_t 41 drivers/gpu/drm/i915/gvt/mmio_context.h i915_reg_t reg; i915_reg_t 216 drivers/gpu/drm/i915/gvt/scheduler.c i915_reg_t reg; i915_reg_t 566 drivers/gpu/drm/i915/i915_cmd_parser.c i915_reg_t addr; i915_reg_t 1158 drivers/gpu/drm/i915/i915_debugfs.c const i915_reg_t reg) i915_reg_t 2378 drivers/gpu/drm/i915/i915_debugfs.c i915_reg_t dc5_reg, dc6_reg = {}; i915_reg_t 2419 drivers/gpu/drm/i915/i915_drv.c i915_reg_t reg = VLV_GTLC_PW_STATUS; i915_reg_t 331 drivers/gpu/drm/i915/i915_drv.h i915_reg_t mmioaddr[20]; i915_reg_t 512 drivers/gpu/drm/i915/i915_drv.h i915_reg_t gpio_reg; i915_reg_t 984 drivers/gpu/drm/i915/i915_drv.h i915_reg_t addr; i915_reg_t 65 drivers/gpu/drm/i915/i915_gem_fence_reg.c i915_reg_t fence_reg_lo, fence_reg_hi; i915_reg_t 152 drivers/gpu/drm/i915/i915_gem_fence_reg.c i915_reg_t reg = FENCE_REG(fence->id); i915_reg_t 184 drivers/gpu/drm/i915/i915_gem_fence_reg.c i915_reg_t reg = FENCE_REG(fence->id); i915_reg_t 1108 drivers/gpu/drm/i915/i915_gpu_error.c i915_reg_t mmio; i915_reg_t 178 drivers/gpu/drm/i915/i915_irq.c void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t 179 drivers/gpu/drm/i915/i915_irq.c i915_reg_t iir, i915_reg_t ier) i915_reg_t 210 drivers/gpu/drm/i915/i915_irq.c static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) i915_reg_t 241 drivers/gpu/drm/i915/i915_irq.c i915_reg_t imr, u32 imr_val, i915_reg_t 242 drivers/gpu/drm/i915/i915_irq.c i915_reg_t ier, u32 ier_val, i915_reg_t 243 drivers/gpu/drm/i915/i915_irq.c i915_reg_t iir) i915_reg_t 330 drivers/gpu/drm/i915/i915_irq.c static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) i915_reg_t 637 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg = PIPESTAT(pipe); i915_reg_t 660 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg = PIPESTAT(pipe); i915_reg_t 766 drivers/gpu/drm/i915/i915_irq.c i915_reg_t high_frame, low_frame; i915_reg_t 1302 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg; i915_reg_t 1729 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg; i915_reg_t 136 drivers/gpu/drm/i915/i915_irq.h void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t 137 drivers/gpu/drm/i915/i915_irq.h i915_reg_t iir, i915_reg_t ier); i915_reg_t 142 drivers/gpu/drm/i915/i915_irq.h i915_reg_t imr, u32 imr_val, i915_reg_t 143 drivers/gpu/drm/i915/i915_irq.h i915_reg_t ier, u32 ier_val, i915_reg_t 144 drivers/gpu/drm/i915/i915_irq.h i915_reg_t iir); i915_reg_t 1647 drivers/gpu/drm/i915/i915_perf.c i915_reg_t reg) i915_reg_t 1684 drivers/gpu/drm/i915/i915_perf.c i915_reg_t flex_regs[] = { i915_reg_t 1711 drivers/gpu/drm/i915/i915_perf.c i915_reg_t reg; i915_reg_t 3128 drivers/gpu/drm/i915/i915_perf.c static const i915_reg_t flex_eu_regs[] = { i915_reg_t 185 drivers/gpu/drm/i915/i915_reg.h #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) i915_reg_t 189 drivers/gpu/drm/i915/i915_reg.h static inline u32 i915_mmio_reg_offset(i915_reg_t reg) i915_reg_t 194 drivers/gpu/drm/i915/i915_reg.h static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) i915_reg_t 199 drivers/gpu/drm/i915/i915_reg.h static inline bool i915_mmio_reg_valid(i915_reg_t reg) i915_reg_t 46 drivers/gpu/drm/i915/i915_sysfs.c i915_reg_t reg) i915_reg_t 868 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace), i915_reg_t 5122 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg, i915_reg_t 5132 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg, i915_reg_t 5836 drivers/gpu/drm/i915/intel_pm.c static const i915_reg_t wm0_pipe_reg[] = { i915_reg_t 9931 drivers/gpu/drm/i915/intel_pm.c const i915_reg_t reg) i915_reg_t 9977 drivers/gpu/drm/i915/intel_pm.c const i915_reg_t reg) i915_reg_t 10052 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg) i915_reg_t 78 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg); i915_reg_t 79 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); i915_reg_t 914 drivers/gpu/drm/i915/intel_uncore.c static const i915_reg_t gen8_shadowed_regs[] = { i915_reg_t 924 drivers/gpu/drm/i915/intel_uncore.c static const i915_reg_t gen11_shadowed_regs[] = { i915_reg_t 938 drivers/gpu/drm/i915/intel_uncore.c static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) i915_reg_t 953 drivers/gpu/drm/i915/intel_uncore.c const i915_reg_t *regs = gen##x##_shadowed_regs; \ i915_reg_t 962 drivers/gpu/drm/i915/intel_uncore.c gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) i915_reg_t 1094 drivers/gpu/drm/i915/intel_uncore.c const i915_reg_t reg, i915_reg_t 1108 drivers/gpu/drm/i915/intel_uncore.c const i915_reg_t reg, i915_reg_t 1137 drivers/gpu/drm/i915/intel_uncore.c gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ i915_reg_t 1145 drivers/gpu/drm/i915/intel_uncore.c gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ i915_reg_t 1210 drivers/gpu/drm/i915/intel_uncore.c func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ i915_reg_t 1222 drivers/gpu/drm/i915/intel_uncore.c func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ i915_reg_t 1247 drivers/gpu/drm/i915/intel_uncore.c gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ i915_reg_t 1255 drivers/gpu/drm/i915/intel_uncore.c gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ i915_reg_t 1289 drivers/gpu/drm/i915/intel_uncore.c gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ i915_reg_t 1302 drivers/gpu/drm/i915/intel_uncore.c func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ i915_reg_t 1314 drivers/gpu/drm/i915/intel_uncore.c func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ i915_reg_t 1359 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg_set, i915_reg_t 1360 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg_ack) i915_reg_t 1803 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t offset_ldw; i915_reg_t 1804 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t offset_udw; i915_reg_t 1897 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, i915_reg_t 1945 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, i915_reg_t 2038 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, unsigned int op) i915_reg_t 81 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r); i915_reg_t 83 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r); i915_reg_t 86 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, bool trace); i915_reg_t 88 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, bool trace); i915_reg_t 90 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, bool trace); i915_reg_t 92 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, bool trace); i915_reg_t 95 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u8 val, bool trace); i915_reg_t 97 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u16 val, bool trace); i915_reg_t 99 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t r, u32 val, bool trace); i915_reg_t 204 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, unsigned int op); i915_reg_t 224 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, i915_reg_t 232 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, i915_reg_t 242 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, i915_reg_t 250 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, i915_reg_t 262 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg) \ i915_reg_t 269 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ i915_reg_t 288 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg) \ i915_reg_t 295 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ i915_reg_t 329 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t lower_reg, i915_reg_t upper_reg) i915_reg_t 379 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 clear, u32 set) i915_reg_t 390 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 clear, u32 set) i915_reg_t 401 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 val, i915_reg_t 65 drivers/gpu/drm/i915/selftests/intel_uncore.c const i915_reg_t *regs; i915_reg_t 71 drivers/gpu/drm/i915/selftests/intel_uncore.c const i915_reg_t *reg; i915_reg_t 190 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); i915_reg_t 282 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t reg = { offset }; i915_reg_t 293 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t reg = { offset }; i915_reg_t 29 drivers/gpu/drm/i915/selftests/mock_uncore.c nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { } i915_reg_t 36 drivers/gpu/drm/i915/selftests/mock_uncore.c nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }