i915_mmio_reg_offset 1002 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); i915_mmio_reg_offset 1004 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); i915_mmio_reg_offset 1020 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); i915_mmio_reg_offset 1022 drivers/gpu/drm/i915/gem/i915_gem_context.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); i915_mmio_reg_offset 1954 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); i915_mmio_reg_offset 599 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); i915_mmio_reg_offset 846 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_CONTEXT_CONTROL(base)); i915_mmio_reg_offset 847 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_HEAD] = i915_mmio_reg_offset(RING_HEAD(base)); i915_mmio_reg_offset 848 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_TAIL] = i915_mmio_reg_offset(RING_TAIL(base)); i915_mmio_reg_offset 849 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_START] = i915_mmio_reg_offset(RING_START(base)); i915_mmio_reg_offset 850 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_CONTROL] = i915_mmio_reg_offset(RING_CTL(base)); i915_mmio_reg_offset 852 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_HEAD_U] = i915_mmio_reg_offset(RING_BBADDR_UDW(base)); i915_mmio_reg_offset 853 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_HEAD_L] = i915_mmio_reg_offset(RING_BBADDR(base)); i915_mmio_reg_offset 854 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_BB_STATE] = i915_mmio_reg_offset(RING_BBSTATE(base)); i915_mmio_reg_offset 856 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_SBBADDR_UDW(base)); i915_mmio_reg_offset 857 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_SECOND_BB_HEAD_L] = i915_mmio_reg_offset(RING_SBBADDR(base)); i915_mmio_reg_offset 858 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_SECOND_BB_STATE] = i915_mmio_reg_offset(RING_SBBSTATE(base)); i915_mmio_reg_offset 861 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_CTX_TIMESTAMP(base)); i915_mmio_reg_offset 862 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP3_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 3)); i915_mmio_reg_offset 863 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP3_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 3)); i915_mmio_reg_offset 864 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP2_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 2)); i915_mmio_reg_offset 865 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP2_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 2)); i915_mmio_reg_offset 866 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP1_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 1)); i915_mmio_reg_offset 867 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP1_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 1)); i915_mmio_reg_offset 868 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP0_UDW] = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0)); i915_mmio_reg_offset 869 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_PDP0_LDW] = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0)); i915_mmio_reg_offset 873 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_INDIRECT_CTX(base)); i915_mmio_reg_offset 875 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(base)); i915_mmio_reg_offset 877 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(base)); i915_mmio_reg_offset 880 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE); i915_mmio_reg_offset 1938 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i)); i915_mmio_reg_offset 1940 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i)); i915_mmio_reg_offset 2010 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); i915_mmio_reg_offset 2016 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); i915_mmio_reg_offset 2025 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); i915_mmio_reg_offset 2098 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = i915_mmio_reg_offset(lri->reg); i915_mmio_reg_offset 3131 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base)); i915_mmio_reg_offset 3133 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); i915_mmio_reg_offset 3136 drivers/gpu/drm/i915/gt/intel_lrc.c i915_mmio_reg_offset(RING_ELSP(base)); i915_mmio_reg_offset 45 drivers/gpu/drm/i915/gt/intel_lrc_reg.h (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \ i915_mmio_reg_offset 456 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); i915_mmio_reg_offset 462 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = i915_mmio_reg_offset(mocs_register(engine, index)); i915_mmio_reg_offset 515 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); i915_mmio_reg_offset 523 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); i915_mmio_reg_offset 530 drivers/gpu/drm/i915/gt/intel_mocs.c *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i)); i915_mmio_reg_offset 1540 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); i915_mmio_reg_offset 1544 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); i915_mmio_reg_offset 1563 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); i915_mmio_reg_offset 1618 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset( i915_mmio_reg_offset 1673 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(last_reg); i915_mmio_reg_offset 1680 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(last_reg); i915_mmio_reg_offset 1714 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); i915_mmio_reg_offset 84 drivers/gpu/drm/i915/gt/intel_workarounds.c unsigned int addr = i915_mmio_reg_offset(wa->reg); i915_mmio_reg_offset 110 drivers/gpu/drm/i915/gt/intel_workarounds.c if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { i915_mmio_reg_offset 112 drivers/gpu/drm/i915/gt/intel_workarounds.c } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { i915_mmio_reg_offset 119 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_->reg), i915_mmio_reg_offset 138 drivers/gpu/drm/i915/gt/intel_workarounds.c GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == i915_mmio_reg_offset 139 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[1].reg)); i915_mmio_reg_offset 140 drivers/gpu/drm/i915/gt/intel_workarounds.c if (i915_mmio_reg_offset(wa_[1].reg) > i915_mmio_reg_offset 141 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[0].reg)) i915_mmio_reg_offset 638 drivers/gpu/drm/i915/gt/intel_workarounds.c *cs++ = i915_mmio_reg_offset(wa->reg); i915_mmio_reg_offset 955 drivers/gpu/drm/i915/gt/intel_workarounds.c name, from, i915_mmio_reg_offset(wa->reg), i915_mmio_reg_offset 1247 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa->reg)); i915_mmio_reg_offset 1253 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(RING_NOPID(base))); i915_mmio_reg_offset 1476 drivers/gpu/drm/i915/gt/intel_workarounds.c if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) i915_mmio_reg_offset 1485 drivers/gpu/drm/i915/gt/intel_workarounds.c u32 offset = i915_mmio_reg_offset(wa->reg); i915_mmio_reg_offset 1542 drivers/gpu/drm/i915/gt/intel_workarounds.c if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) i915_mmio_reg_offset 135 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); i915_mmio_reg_offset 162 drivers/gpu/drm/i915/gt/selftest_workarounds.c return i915_mmio_reg_offset(reg); i915_mmio_reg_offset 428 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); i915_mmio_reg_offset 482 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); i915_mmio_reg_offset 787 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); i915_mmio_reg_offset 828 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); i915_mmio_reg_offset 878 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 offset = i915_mmio_reg_offset(reg); i915_mmio_reg_offset 882 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(tbl->reg) == offset) i915_mmio_reg_offset 906 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(reg), a, b); i915_mmio_reg_offset 928 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(reg), a); i915_mmio_reg_offset 960 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (i915_mmio_reg_offset(wa->reg) & i915_mmio_reg_offset 43 drivers/gpu/drm/i915/gt/uc/intel_guc.c i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); i915_mmio_reg_offset 46 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); i915_mmio_reg_offset 394 drivers/gpu/drm/i915/gt/uc/intel_uc.c i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET), i915_mmio_reg_offset 397 drivers/gpu/drm/i915/gt/uc/intel_uc.c i915_mmio_reg_offset(GUC_WOPCM_SIZE), i915_mmio_reg_offset 852 drivers/gpu/drm/i915/gvt/cmd_parser.c nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); i915_mmio_reg_offset 911 drivers/gpu/drm/i915/gvt/cmd_parser.c if (offset == i915_mmio_reg_offset(DERRMR) || i915_mmio_reg_offset 912 drivers/gpu/drm/i915/gvt/cmd_parser.c offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { i915_mmio_reg_offset 982 drivers/gpu/drm/i915/gvt/cmd_parser.c cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR)) i915_mmio_reg_offset 377 drivers/gpu/drm/i915/gvt/edid.c if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) i915_mmio_reg_offset 379 drivers/gpu/drm/i915/gvt/edid.c else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) i915_mmio_reg_offset 405 drivers/gpu/drm/i915/gvt/edid.c if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) i915_mmio_reg_offset 407 drivers/gpu/drm/i915/gvt/edid.c else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) i915_mmio_reg_offset 409 drivers/gpu/drm/i915/gvt/edid.c else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) i915_mmio_reg_offset 411 drivers/gpu/drm/i915/gvt/edid.c else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) i915_mmio_reg_offset 446 drivers/gpu/drm/i915/gvt/gvt.h (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) i915_mmio_reg_offset 450 drivers/gpu/drm/i915/gvt/gvt.h (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) i915_mmio_reg_offset 167 drivers/gpu/drm/i915/gvt/handlers.c ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) i915_mmio_reg_offset 170 drivers/gpu/drm/i915/gvt/handlers.c (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) i915_mmio_reg_offset 526 drivers/gpu/drm/i915/gvt/handlers.c reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) { i915_mmio_reg_offset 545 drivers/gpu/drm/i915/gvt/handlers.c if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) i915_mmio_reg_offset 627 drivers/gpu/drm/i915/gvt/handlers.c end = i915_mmio_reg_offset(i915_end); i915_mmio_reg_offset 1654 drivers/gpu/drm/i915/gvt/handlers.c offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || i915_mmio_reg_offset 1655 drivers/gpu/drm/i915/gvt/handlers.c offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { i915_mmio_reg_offset 1811 drivers/gpu/drm/i915/gvt/handlers.c ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ i915_mmio_reg_offset 3298 drivers/gpu/drm/i915/gvt/handlers.c if (offset >= i915_mmio_reg_offset(block->offset) && i915_mmio_reg_offset 3299 drivers/gpu/drm/i915/gvt/handlers.c offset < i915_mmio_reg_offset(block->offset) + block->size) i915_mmio_reg_offset 3422 drivers/gpu/drm/i915/gvt/handlers.c i915_mmio_reg_offset(block->offset) + j, i915_mmio_reg_offset 154 drivers/gpu/drm/i915/gvt/interrupt.c if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) i915_mmio_reg_offset 329 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) i915_mmio_reg_offset 331 drivers/gpu/drm/i915/gvt/interrupt.c regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); i915_mmio_reg_offset 357 drivers/gpu/drm/i915/gvt/interrupt.c u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); i915_mmio_reg_offset 363 drivers/gpu/drm/i915/gvt/interrupt.c i915_mmio_reg_offset(up_irq_info->reg_base)); i915_mmio_reg_offset 365 drivers/gpu/drm/i915/gvt/interrupt.c i915_mmio_reg_offset(up_irq_info->reg_base)); i915_mmio_reg_offset 411 drivers/gpu/drm/i915/gvt/interrupt.c reg_base = i915_mmio_reg_offset(info->reg_base); i915_mmio_reg_offset 469 drivers/gpu/drm/i915/gvt/interrupt.c if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & i915_mmio_reg_offset 480 drivers/gpu/drm/i915/gvt/interrupt.c reg_base = i915_mmio_reg_offset(info->reg_base); i915_mmio_reg_offset 486 drivers/gpu/drm/i915/gvt/interrupt.c if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) i915_mmio_reg_offset 220 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = i915_mmio_reg_offset(mmio->reg); i915_mmio_reg_offset 251 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); i915_mmio_reg_offset 278 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); i915_mmio_reg_offset 533 drivers/gpu/drm/i915/gvt/mmio_context.c i915_mmio_reg_offset(mmio->reg), i915_mmio_reg_offset 91 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL0), i915_mmio_reg_offset 92 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL1), i915_mmio_reg_offset 93 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL2), i915_mmio_reg_offset 94 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL3), i915_mmio_reg_offset 95 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL4), i915_mmio_reg_offset 96 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL5), i915_mmio_reg_offset 97 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(EU_PERF_CNTL6), i915_mmio_reg_offset 113 drivers/gpu/drm/i915/gvt/scheduler.c i915_mmio_reg_offset(GEN8_OACTXCONTROL); i915_mmio_reg_offset 219 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); i915_mmio_reg_offset 221 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); i915_mmio_reg_offset 223 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); i915_mmio_reg_offset 829 drivers/gpu/drm/i915/i915_cmd_parser.c u32 curr = i915_mmio_reg_offset(reg_table[i].addr); i915_mmio_reg_offset 1103 drivers/gpu/drm/i915/i915_cmd_parser.c int ret = addr - i915_mmio_reg_offset(table[mid].addr); i915_mmio_reg_offset 2892 drivers/gpu/drm/i915/i915_debugfs.c i915_mmio_reg_offset(wa->reg), i915_mmio_reg_offset 218 drivers/gpu/drm/i915/i915_irq.c i915_mmio_reg_offset(reg), val); i915_mmio_reg_offset 233 drivers/gpu/drm/i915/i915_irq.c i915_mmio_reg_offset(GEN2_IIR), val); i915_mmio_reg_offset 1649 drivers/gpu/drm/i915/i915_perf.c u32 mmio = i915_mmio_reg_offset(reg); i915_mmio_reg_offset 1661 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio) i915_mmio_reg_offset 1756 drivers/gpu/drm/i915/i915_perf.c *cs++ = i915_mmio_reg_offset(flex->reg); i915_mmio_reg_offset 3140 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr) i915_mmio_reg_offset 3148 drivers/gpu/drm/i915/i915_perf.c return (addr >= i915_mmio_reg_offset(OASTARTTRIG1) && i915_mmio_reg_offset 3149 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OASTARTTRIG8)) || i915_mmio_reg_offset 3150 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(OAREPORTTRIG1) && i915_mmio_reg_offset 3151 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OAREPORTTRIG8)) || i915_mmio_reg_offset 3152 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(OACEC0_0) && i915_mmio_reg_offset 3153 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OACEC7_1)); i915_mmio_reg_offset 3158 drivers/gpu/drm/i915/i915_perf.c return addr == i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) || i915_mmio_reg_offset 3159 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(MICRO_BP0_0) && i915_mmio_reg_offset 3160 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(NOA_WRITE)) || i915_mmio_reg_offset 3161 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(OA_PERFCNT1_LO) && i915_mmio_reg_offset 3162 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OA_PERFCNT2_HI)) || i915_mmio_reg_offset 3163 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(OA_PERFMATRIX_LO) && i915_mmio_reg_offset 3164 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OA_PERFMATRIX_HI)); i915_mmio_reg_offset 3170 drivers/gpu/drm/i915/i915_perf.c addr == i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) || i915_mmio_reg_offset 3171 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(RPM_CONFIG0) && i915_mmio_reg_offset 3172 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(NOA_CONFIG(8))); i915_mmio_reg_offset 3178 drivers/gpu/drm/i915/i915_perf.c addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) || i915_mmio_reg_offset 3179 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) && i915_mmio_reg_offset 3180 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI)); i915_mmio_reg_offset 3187 drivers/gpu/drm/i915/i915_perf.c (addr >= i915_mmio_reg_offset(HSW_MBVID2_NOA0) && i915_mmio_reg_offset 3188 drivers/gpu/drm/i915/i915_perf.c addr <= i915_mmio_reg_offset(HSW_MBVID2_NOA9)) || i915_mmio_reg_offset 3189 drivers/gpu/drm/i915/i915_perf.c addr == i915_mmio_reg_offset(HSW_MBVID2_MISR0); i915_mmio_reg_offset 3204 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg) i915_mmio_reg_offset 3211 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg) i915_mmio_reg_offset 196 drivers/gpu/drm/i915/i915_reg.h return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); i915_mmio_reg_offset 883 drivers/gpu/drm/i915/i915_trace.h __entry->reg = i915_mmio_reg_offset(reg); i915_mmio_reg_offset 9996 drivers/gpu/drm/i915/intel_pm.c i = (i915_mmio_reg_offset(reg) - i915_mmio_reg_offset 9997 drivers/gpu/drm/i915/intel_pm.c i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); i915_mmio_reg_offset 940 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(*reg); i915_mmio_reg_offset 1101 drivers/gpu/drm/i915/intel_uncore.c i915_mmio_reg_offset(reg))) i915_mmio_reg_offset 1168 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(reg); \ i915_mmio_reg_offset 1223 drivers/gpu/drm/i915/intel_uncore.c return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ i915_mmio_reg_offset 1276 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(reg); \ i915_mmio_reg_offset 1315 drivers/gpu/drm/i915/intel_uncore.c return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ i915_mmio_reg_offset 1379 drivers/gpu/drm/i915/intel_uncore.c d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); i915_mmio_reg_offset 1380 drivers/gpu/drm/i915/intel_uncore.c d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); i915_mmio_reg_offset 1829 drivers/gpu/drm/i915/intel_uncore.c u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); i915_mmio_reg_offset 264 drivers/gpu/drm/i915/intel_uncore.h return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \ i915_mmio_reg_offset 271 drivers/gpu/drm/i915/intel_uncore.h write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \ i915_mmio_reg_offset 413 drivers/gpu/drm/i915/intel_uncore.h readl(base + i915_mmio_reg_offset(reg)) i915_mmio_reg_offset 415 drivers/gpu/drm/i915/intel_uncore.h writel(value, base + i915_mmio_reg_offset(reg)) i915_mmio_reg_offset 78 drivers/gpu/drm/i915/selftests/intel_uncore.c u32 offset = i915_mmio_reg_offset(*reg);