i915_ggtt_offset 1523 drivers/gpu/drm/i915/display/intel_display_types.h return i915_ggtt_offset(state->vma); i915_ggtt_offset 257 drivers/gpu/drm/i915/display/intel_fbc.c i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); i915_ggtt_offset 265 drivers/gpu/drm/i915/display/intel_fbdev.c i915_ggtt_offset(vma)); i915_ggtt_offset 800 drivers/gpu/drm/i915/display/intel_overlay.c iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); i915_ggtt_offset 817 drivers/gpu/drm/i915/display/intel_overlay.c iowrite32(i915_ggtt_offset(vma) + params->offset_U, i915_ggtt_offset 819 drivers/gpu/drm/i915/display/intel_overlay.c iowrite32(i915_ggtt_offset(vma) + params->offset_V, i915_ggtt_offset 1325 drivers/gpu/drm/i915/display/intel_overlay.c overlay->flip_addr = i915_ggtt_offset(vma); i915_ggtt_offset 1118 drivers/gpu/drm/i915/gem/i915_gem_context.c offset = i915_ggtt_offset(ce->state) + i915_ggtt_offset 214 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); i915_ggtt_offset 215 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); i915_ggtt_offset 220 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c *cs++ = i915_ggtt_offset(vma) + offset; i915_ggtt_offset 224 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c *cs++ = i915_ggtt_offset(vma) + offset; i915_ggtt_offset 1293 drivers/gpu/drm/i915/gt/intel_engine_cs.c i915_ggtt_offset(rq->ring->vma), i915_ggtt_offset 1305 drivers/gpu/drm/i915/gt/intel_engine_cs.c i915_ggtt_offset(rq->ring->vma), i915_ggtt_offset 1389 drivers/gpu/drm/i915/gt/intel_engine_cs.c i915_ggtt_offset(rq->ring->vma)); i915_ggtt_offset 1536 drivers/gpu/drm/i915/gt/intel_engine_cs.c return ring == i915_ggtt_offset(rq->ring->vma); i915_ggtt_offset 50 drivers/gpu/drm/i915/gt/intel_gt.h return i915_ggtt_offset(gt->scratch) + field; i915_ggtt_offset 246 drivers/gpu/drm/i915/gt/intel_lrc.c return (i915_ggtt_offset(engine->status_page.vma) + i915_ggtt_offset 447 drivers/gpu/drm/i915/gt/intel_lrc.c desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; i915_ggtt_offset 1772 drivers/gpu/drm/i915/gt/intel_lrc.c regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); i915_ggtt_offset 2337 drivers/gpu/drm/i915/gt/intel_lrc.c i915_ggtt_offset(engine->status_page.vma)); i915_ggtt_offset 3236 drivers/gpu/drm/i915/gt/intel_lrc.c u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); i915_ggtt_offset 3248 drivers/gpu/drm/i915/gt/intel_lrc.c u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); i915_ggtt_offset 118 drivers/gpu/drm/i915/gt/intel_renderstate.c so->batch_offset = i915_ggtt_offset(so->vma); i915_ggtt_offset 595 drivers/gpu/drm/i915/gt/intel_ringbuffer.c set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); i915_ggtt_offset 689 drivers/gpu/drm/i915/gt/intel_ringbuffer.c ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); i915_ggtt_offset 716 drivers/gpu/drm/i915/gt/intel_ringbuffer.c i915_ggtt_offset(ring->vma)); i915_ggtt_offset 1648 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_ggtt_offset(engine->kernel_context->state) | i915_ggtt_offset 1655 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; i915_ggtt_offset 325 drivers/gpu/drm/i915/gt/intel_timeline.c i915_ggtt_offset(tl->hwsp_ggtt) + i915_ggtt_offset 462 drivers/gpu/drm/i915/gt/intel_timeline.c tl->hwsp_offset += i915_ggtt_offset(vma); i915_ggtt_offset 517 drivers/gpu/drm/i915/gt/intel_timeline.c *hwsp = i915_ggtt_offset(cl->hwsp->vma) + i915_ggtt_offset 1492 drivers/gpu/drm/i915/gt/intel_workarounds.c *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; i915_ggtt_offset 98 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma) + 4 * idx; i915_ggtt_offset 103 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); i915_ggtt_offset 166 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); i915_ggtt_offset 395 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma); i915_ggtt_offset 406 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma); i915_ggtt_offset 439 drivers/gpu/drm/i915/gt/selftest_lrc.c *cs++ = i915_ggtt_offset(vma); i915_ggtt_offset 136 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; i915_ggtt_offset 128 drivers/gpu/drm/i915/gt/uc/intel_guc.h u32 offset = i915_ggtt_offset(vma); i915_ggtt_offset 498 drivers/gpu/drm/i915/gvt/scheduler.c bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); i915_ggtt_offset 566 drivers/gpu/drm/i915/gvt/scheduler.c wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); i915_ggtt_offset 353 drivers/gpu/drm/i915/i915_gem.c node.start = i915_ggtt_offset(vma); i915_ggtt_offset 563 drivers/gpu/drm/i915/i915_gem.c node.start = i915_ggtt_offset(vma); i915_ggtt_offset 1039 drivers/gpu/drm/i915/i915_gem.c i915_ggtt_offset(vma), alignment, i915_ggtt_offset 1822 drivers/gpu/drm/i915/i915_gem_gtt.c u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; i915_ggtt_offset 1179 drivers/gpu/drm/i915/i915_gpu_error.c erq->start = i915_ggtt_offset(request->ring->vma); i915_ggtt_offset 527 drivers/gpu/drm/i915/i915_perf.c u32 gtt_offset = i915_ggtt_offset(vma); i915_ggtt_offset 661 drivers/gpu/drm/i915/i915_perf.c u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); i915_ggtt_offset 949 drivers/gpu/drm/i915/i915_perf.c u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); i915_ggtt_offset 1264 drivers/gpu/drm/i915/i915_perf.c stream->specific_ctx_id = i915_ggtt_offset(ce->state); i915_ggtt_offset 1396 drivers/gpu/drm/i915/i915_perf.c u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); i915_ggtt_offset 1446 drivers/gpu/drm/i915/i915_perf.c u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); i915_ggtt_offset 1545 drivers/gpu/drm/i915/i915_perf.c i915_ggtt_offset(stream->oa_buffer.vma), i915_ggtt_offset 1728 drivers/gpu/drm/i915/i915_perf.c offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;