i915_enable_pipestat 1651 drivers/gpu/drm/i915/display/intel_tv.c 		i915_enable_pipestat(dev_priv, 0,
i915_enable_pipestat  699 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
i915_enable_pipestat  701 drivers/gpu/drm/i915/i915_irq.c 		i915_enable_pipestat(dev_priv, PIPE_A,
i915_enable_pipestat 2949 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
i915_enable_pipestat 2972 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, pipe,
i915_enable_pipestat 3192 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
i915_enable_pipestat 3194 drivers/gpu/drm/i915/i915_irq.c 		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
i915_enable_pipestat 3931 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat 3932 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat 4105 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat 4106 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat 4222 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
i915_enable_pipestat 4223 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat 4224 drivers/gpu/drm/i915/i915_irq.c 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat   36 drivers/gpu/drm/i915/i915_irq.h i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,