hwsq_reg 21 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h static inline struct hwsq_reg hwsq_reg 24 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h return (struct hwsq_reg) { hwsq_reg 34 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h static inline struct hwsq_reg hwsq_reg 37 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h return (struct hwsq_reg) { hwsq_reg 47 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h static inline struct hwsq_reg hwsq_reg 50 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h return (struct hwsq_reg) { hwsq_reg 86 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) hwsq_reg 95 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) hwsq_reg 111 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg) hwsq_reg 117 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) hwsq_reg 522 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_fifo = hwsq_reg(0x002504); hwsq_reg 523 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_spll[0] = hwsq_reg(0x004020); hwsq_reg 524 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_spll[1] = hwsq_reg(0x004024); hwsq_reg 525 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028); hwsq_reg 526 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); hwsq_reg 531 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_divs = hwsq_reg(0x004800); hwsq_reg 534 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_divs = hwsq_reg(0x004700); hwsq_reg 537 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c clk->hwsq.r_mast = hwsq_reg(0x00c040); hwsq_reg 11 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq_reg r_fifo; hwsq_reg 12 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq_reg r_spll[2]; hwsq_reg 13 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq_reg r_nvpll[2]; hwsq_reg 14 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq_reg r_divs; hwsq_reg 15 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h struct hwsq_reg r_mast; hwsq_reg 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x002504; hwsq_reg 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x004008; hwsq_reg 42 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x00400c; hwsq_reg 43 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x00c040; hwsq_reg 44 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100200; hwsq_reg 45 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100210; hwsq_reg 46 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x10021c; hwsq_reg 47 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x1002d0; hwsq_reg 48 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x1002d4; hwsq_reg 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x1002dc; hwsq_reg 50 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x10053c; hwsq_reg 51 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x1005a0; hwsq_reg 52 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x1005a4; hwsq_reg 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100710; hwsq_reg 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100714; hwsq_reg 55 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100718; hwsq_reg 56 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x10071c; hwsq_reg 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100da0; hwsq_reg 58 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100e20; hwsq_reg 59 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x100e24; hwsq_reg 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_0x611200; hwsq_reg 61 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_timing[9]; hwsq_reg 62 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_mr[4]; hwsq_reg 63 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c struct hwsq_reg r_gpio[4]; hwsq_reg 599 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x002504 = hwsq_reg(0x002504); hwsq_reg 600 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); hwsq_reg 601 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x004008 = hwsq_reg(0x004008); hwsq_reg 602 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); hwsq_reg 603 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100200 = hwsq_reg(0x100200); hwsq_reg 604 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100210 = hwsq_reg(0x100210); hwsq_reg 605 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x10021c = hwsq_reg(0x10021c); hwsq_reg 606 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); hwsq_reg 607 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); hwsq_reg 608 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); hwsq_reg 609 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x10053c = hwsq_reg(0x10053c); hwsq_reg 610 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0); hwsq_reg 611 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4); hwsq_reg 612 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100710 = hwsq_reg(0x100710); hwsq_reg 613 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100714 = hwsq_reg(0x100714); hwsq_reg 614 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100718 = hwsq_reg(0x100718); hwsq_reg 615 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x10071c = hwsq_reg(0x10071c); hwsq_reg 617 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); hwsq_reg 618 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); hwsq_reg 619 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_0x611200 = hwsq_reg(0x611200); hwsq_reg 622 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); hwsq_reg 630 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); hwsq_reg 631 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); hwsq_reg 632 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); hwsq_reg 633 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); hwsq_reg 636 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104); hwsq_reg 637 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108); hwsq_reg 638 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120); hwsq_reg 639 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124);