hwsq               37 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
hwsq               39 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
hwsq               40 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq->c.size += size;
hwsq               46 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	struct nvkm_hwsq *hwsq;
hwsq               48 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
hwsq               49 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	if (hwsq) {
hwsq               50 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq->subdev = subdev;
hwsq               51 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq->addr = ~0;
hwsq               52 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq->data = ~0;
hwsq               53 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
hwsq               54 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq->c.size = 0;
hwsq               57 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	return hwsq ? 0 : -ENOMEM;
hwsq               63 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	struct nvkm_hwsq *hwsq = *phwsq;
hwsq               65 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	if (hwsq) {
hwsq               66 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		struct nvkm_subdev *subdev = hwsq->subdev;
hwsq               68 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq->c.size = (hwsq->c.size + 4) / 4;
hwsq               69 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		if (hwsq->c.size <= bus->func->hwsq_size) {
hwsq               72 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 							   (u32 *)hwsq->c.data,
hwsq               73 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 								  hwsq->c.size);
hwsq               81 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		for (i = 0; ret && i < hwsq->c.size; i++)
hwsq               82 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 			nvkm_error(subdev, "\t%08x\n", ((u32 *)hwsq->c.data)[i]);
hwsq               85 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		kfree(hwsq);
hwsq               91 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
hwsq               93 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);
hwsq               95 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	if (hwsq->data != data) {
hwsq               96 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
hwsq               97 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 			hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,
hwsq              100 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 			hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });
hwsq              104 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {
hwsq              105 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,
hwsq              108 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 		hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });
hwsq              111 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq->addr = addr;
hwsq              112 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq->data = data;
hwsq              116 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
hwsq              118 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);
hwsq              124 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq_cmd(hwsq, 1, (u8[]){ flag });
hwsq              128 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
hwsq              130 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);
hwsq              131 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
hwsq              135 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c nvkm_hwsq_wait_vblank(struct nvkm_hwsq *hwsq)
hwsq              137 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	struct nvkm_subdev *subdev = hwsq->subdev;
hwsq              162 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x0);
hwsq              163 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x1);
hwsq              167 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
hwsq              175 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	nvkm_debug(hwsq->subdev, "    DELAY = %d ns\n", nsec);
hwsq              176 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c 	hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
hwsq                8 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	struct nvkm_hwsq *hwsq;
hwsq               61 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
hwsq               65 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	ret = nvkm_hwsq_init(subdev, &ram->hwsq);
hwsq               75 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_exec(struct hwsq *ram, bool exec)
hwsq               79 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 		ret = nvkm_hwsq_fini(&ram->hwsq, exec);
hwsq               86 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
hwsq               95 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
hwsq              104 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 			nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data);
hwsq              111 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
hwsq              117 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
hwsq              126 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_setf(struct hwsq *ram, u8 flag, int data)
hwsq              128 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	nvkm_hwsq_setf(ram->hwsq, flag, data);
hwsq              132 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
hwsq              134 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	nvkm_hwsq_wait(ram->hwsq, flag, data);
hwsq              138 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wait_vblank(struct hwsq *ram)
hwsq              140 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	nvkm_hwsq_wait_vblank(ram->hwsq);
hwsq              144 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_nsec(struct hwsq *ram, u32 nsec)
hwsq              146 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h 	nvkm_hwsq_nsec(ram->hwsq, nsec);
hwsq              371 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	struct nv50_clk_hwsq *hwsq = &clk->hwsq;
hwsq              384 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	out = clk_init(hwsq, subdev);
hwsq              388 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
hwsq              389 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_nsec(hwsq, 8000);
hwsq              390 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_setf(hwsq, 0x10, 0x00); /* disable fb */
hwsq              391 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
hwsq              446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, mast, mastm, 0x00000000);
hwsq              447 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, divs, divsm, divsv);
hwsq              448 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, mast, mastm, mastv);
hwsq              454 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
hwsq              456 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
hwsq              463 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, nvpll[0], 0xc03f0100,
hwsq              465 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
hwsq              474 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
hwsq              475 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x00100033, 0x00000023);
hwsq              481 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, spll[0], 0xc03f0100,
hwsq              483 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
hwsq              484 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk_mask(hwsq, mast, 0x00100033, 0x00000033);
hwsq              488 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_setf(hwsq, 0x10, 0x01); /* enable fb */
hwsq              489 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
hwsq              490 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
hwsq              498 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	return clk_exec(&clk->hwsq, true);
hwsq              505 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk_exec(&clk->hwsq, false);
hwsq              522 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_fifo = hwsq_reg(0x002504);
hwsq              523 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_spll[0] = hwsq_reg(0x004020);
hwsq              524 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_spll[1] = hwsq_reg(0x004024);
hwsq              525 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
hwsq              526 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
hwsq              531 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk->hwsq.r_divs = hwsq_reg(0x004800);
hwsq              534 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		clk->hwsq.r_divs = hwsq_reg(0x004700);
hwsq              537 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	clk->hwsq.r_mast = hwsq_reg(0x00c040);
hwsq               10 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h 	struct hwsq base;
hwsq               20 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h 	struct nv50_clk_hwsq hwsq;
hwsq               39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	struct hwsq base;
hwsq               68 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	struct nv50_ramseq hwsq;
hwsq              184 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq)
hwsq              186 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, mr[0], 0x100, 0x100);
hwsq              187 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, mr[0], 0x100, 0x000);
hwsq              188 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 24000);
hwsq              192 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val)
hwsq              194 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio;
hwsq              206 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		gpio_val = ram_rd32(hwsq, gpio[reg]);
hwsq              213 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));
hwsq              214 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_nsec(hwsq, 20000);
hwsq              222 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	struct nv50_ramseq *hwsq = &ram->hwsq;
hwsq              282 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ret = ram_init(hwsq, subdev);
hwsq              287 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->base.mr[0] = ram_rd32(hwsq, mr[0]);
hwsq              288 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->base.mr[1] = ram_rd32(hwsq, mr[1]);
hwsq              289 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->base.mr[2] = ram_rd32(hwsq, mr[2]);
hwsq              306 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000);
hwsq              309 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000);
hwsq              311 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wait_vblank(hwsq);
hwsq              312 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x611200, 0x00003300);
hwsq              313 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */
hwsq              314 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 8000);
hwsq              315 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_setf(hwsq, 0x10, 0x00); /* disable fb */
hwsq              316 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
hwsq              317 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 2000);
hwsq              320 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		nv50_ram_gpio(hwsq, 0x2e, 1);
hwsq              322 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
hwsq              323 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
hwsq              324 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
hwsq              325 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */
hwsq              326 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */
hwsq              351 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
hwsq              354 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 |
hwsq              356 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
hwsq              357 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x004008, 0x91ff0000, r004008);
hwsq              361 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_wr32(hwsq, 0x100da0, r100da0);
hwsq              363 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ);
hwsq              364 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 64000); /*XXX*/
hwsq              365 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 32000); /*XXX*/
hwsq              367 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
hwsq              369 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
hwsq              370 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */
hwsq              371 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
hwsq              373 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_nsec(hwsq, 12000);
hwsq              377 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_nuke(hwsq, mr[0]); /* force update */
hwsq              378 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, mr[0], 0x000, 0x000);
hwsq              381 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_nuke(hwsq, mr[1]); /* force update */
hwsq              382 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_wr32(hwsq, mr[1], ram->base.mr[1]);
hwsq              383 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_nuke(hwsq, mr[0]); /* force update */
hwsq              384 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_wr32(hwsq, mr[0], ram->base.mr[0]);
hwsq              390 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);
hwsq              391 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);
hwsq              392 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);
hwsq              393 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);
hwsq              394 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);
hwsq              395 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);
hwsq              396 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);
hwsq              397 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);
hwsq              398 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);
hwsq              401 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000);
hwsq              402 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12);
hwsq              405 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	unk710  = ram_rd32(hwsq, 0x100710) & ~0x00000100;
hwsq              406 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	unk714  = ram_rd32(hwsq, 0x100714) & ~0xf0000020;
hwsq              407 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	unk718  = ram_rd32(hwsq, 0x100718) & ~0x00000100;
hwsq              408 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	unk71c  = ram_rd32(hwsq, 0x10071c) & ~0x00000100;
hwsq              437 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x100714, 0xffffffff, unk714);
hwsq              438 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c);
hwsq              439 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x100718, 0xffffffff, unk718);
hwsq              440 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x100710, 0xffffffff, unk710);
hwsq              445 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 |
hwsq              448 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 |
hwsq              450 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000);
hwsq              452 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000);
hwsq              454 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]);
hwsq              457 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		nv50_ram_gpio(hwsq, 0x2e, 0);
hwsq              461 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		nvkm_sddr2_dll_reset(hwsq);
hwsq              463 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_setf(hwsq, 0x10, 0x01); /* enable fb */
hwsq              464 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
hwsq              465 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x611200, 0x00003330);
hwsq              466 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
hwsq              469 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800);
hwsq              471 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000);
hwsq              473 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000);
hwsq              475 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200);
hwsq              485 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true));
hwsq              493 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_exec(&ram->hwsq, false);
hwsq              599 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x002504 = hwsq_reg(0x002504);
hwsq              600 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
hwsq              601 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
hwsq              602 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
hwsq              603 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100200 = hwsq_reg(0x100200);
hwsq              604 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
hwsq              605 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x10021c = hwsq_reg(0x10021c);
hwsq              606 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
hwsq              607 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
hwsq              608 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
hwsq              609 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x10053c = hwsq_reg(0x10053c);
hwsq              610 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0);
hwsq              611 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4);
hwsq              612 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100710 = hwsq_reg(0x100710);
hwsq              613 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100714 = hwsq_reg(0x100714);
hwsq              614 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100718 = hwsq_reg(0x100718);
hwsq              615 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x10071c = hwsq_reg(0x10071c);
hwsq              616 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask);
hwsq              617 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
hwsq              618 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
hwsq              619 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_0x611200 = hwsq_reg(0x611200);
hwsq              622 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));
hwsq              625 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);
hwsq              626 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);
hwsq              627 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);
hwsq              628 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);
hwsq              630 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);
hwsq              631 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);
hwsq              632 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);
hwsq              633 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 		ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);
hwsq              636 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104);
hwsq              637 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108);
hwsq              638 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120);
hwsq              639 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124);