CLK_MUX_HIWORD_MASK 110 drivers/clk/clk-mux.c if (mux->flags & CLK_MUX_HIWORD_MASK) { CLK_MUX_HIWORD_MASK 160 drivers/clk/clk-mux.c if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { CLK_MUX_HIWORD_MASK 96 drivers/clk/hisilicon/clk-hi3620.c { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 97 drivers/clk/hisilicon/clk-hi3620.c { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 98 drivers/clk/hisilicon/clk-hi3620.c { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 99 drivers/clk/hisilicon/clk-hi3620.c { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 100 drivers/clk/hisilicon/clk-hi3620.c { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 101 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 102 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 103 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 104 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 105 drivers/clk/hisilicon/clk-hi3620.c { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 106 drivers/clk/hisilicon/clk-hi3620.c { HI3620_PWM1_MUX, "pwm1_mux", pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), CLK_SET_RATE_PARENT, 0x104, 11, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 107 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SD_MUX, "sd_mux", sd_mux_p, ARRAY_SIZE(sd_mux_p), CLK_SET_RATE_PARENT, 0x108, 4, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 108 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC1_MUX, "mmc1_mux", mmc1_mux_p, ARRAY_SIZE(mmc1_mux_p), CLK_SET_RATE_PARENT, 0x108, 9, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 109 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC1_MUX2, "mmc1_mux2", mmc1_mux2_p, ARRAY_SIZE(mmc1_mux2_p), CLK_SET_RATE_PARENT, 0x108, 10, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 110 drivers/clk/hisilicon/clk-hi3620.c { HI3620_G2D_MUX, "g2d_mux", g2d_mux_p, ARRAY_SIZE(g2d_mux_p), CLK_SET_RATE_PARENT, 0x10c, 5, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 111 drivers/clk/hisilicon/clk-hi3620.c { HI3620_VENC_MUX, "venc_mux", venc_mux_p, ARRAY_SIZE(venc_mux_p), CLK_SET_RATE_PARENT, 0x10c, 11, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 112 drivers/clk/hisilicon/clk-hi3620.c { HI3620_VDEC_MUX, "vdec_mux", vdec_mux_p, ARRAY_SIZE(vdec_mux_p), CLK_SET_RATE_PARENT, 0x110, 5, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 113 drivers/clk/hisilicon/clk-hi3620.c { HI3620_VPP_MUX, "vpp_mux", vpp_mux_p, ARRAY_SIZE(vpp_mux_p), CLK_SET_RATE_PARENT, 0x110, 11, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 114 drivers/clk/hisilicon/clk-hi3620.c { HI3620_EDC0_MUX, "edc0_mux", edc0_mux_p, ARRAY_SIZE(edc0_mux_p), CLK_SET_RATE_PARENT, 0x114, 6, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 115 drivers/clk/hisilicon/clk-hi3620.c { HI3620_LDI0_MUX, "ldi0_mux", ldi0_mux_p, ARRAY_SIZE(ldi0_mux_p), CLK_SET_RATE_PARENT, 0x114, 13, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 116 drivers/clk/hisilicon/clk-hi3620.c { HI3620_EDC1_MUX, "edc1_mux", edc1_mux_p, ARRAY_SIZE(edc1_mux_p), CLK_SET_RATE_PARENT, 0x118, 6, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 117 drivers/clk/hisilicon/clk-hi3620.c { HI3620_LDI1_MUX, "ldi1_mux", ldi1_mux_p, ARRAY_SIZE(ldi1_mux_p), CLK_SET_RATE_PARENT, 0x118, 14, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 118 drivers/clk/hisilicon/clk-hi3620.c { HI3620_RCLK_HSIC, "rclk_hsic", rclk_hsic_p, ARRAY_SIZE(rclk_hsic_p), CLK_SET_RATE_PARENT, 0x130, 2, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 119 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), CLK_SET_RATE_PARENT, 0x140, 4, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 120 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 271 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 274 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 277 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 280 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 283 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 286 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 289 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 292 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 295 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 298 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 301 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 304 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 307 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 310 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 313 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 316 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 319 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 322 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 325 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 328 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 331 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 441 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 444 drivers/clk/hisilicon/clk-hi3660.c CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 420 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 423 drivers/clk/hisilicon/clk-hi3670.c 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 426 drivers/clk/hisilicon/clk-hi3670.c 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 429 drivers/clk/hisilicon/clk-hi3670.c 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 432 drivers/clk/hisilicon/clk-hi3670.c 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 435 drivers/clk/hisilicon/clk-hi3670.c 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 438 drivers/clk/hisilicon/clk-hi3670.c 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 441 drivers/clk/hisilicon/clk-hi3670.c 0x100, 0, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 444 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 447 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 450 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 453 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 456 drivers/clk/hisilicon/clk-hi3670.c 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 459 drivers/clk/hisilicon/clk-hi3670.c 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 462 drivers/clk/hisilicon/clk-hi3670.c 0x100, 6, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 465 drivers/clk/hisilicon/clk-hi3670.c 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 468 drivers/clk/hisilicon/clk-hi3670.c 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 471 drivers/clk/hisilicon/clk-hi3670.c 0x108, 3, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 474 drivers/clk/hisilicon/clk-hi3670.c 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 477 drivers/clk/hisilicon/clk-hi3670.c 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 480 drivers/clk/hisilicon/clk-hi3670.c 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 483 drivers/clk/hisilicon/clk-hi3670.c 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 636 drivers/clk/hisilicon/clk-hi3670.c 0x274, 8, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 639 drivers/clk/hisilicon/clk-hi3670.c 0x254, 12, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 642 drivers/clk/hisilicon/clk-hi3670.c 0x254, 14, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 645 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 648 drivers/clk/hisilicon/clk-hi3670.c 0x268, 9, 2, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 785 drivers/clk/hisilicon/clk-hi3670.c 0x74, 6, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 788 drivers/clk/hisilicon/clk-hi3670.c 0x68, 6, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 791 drivers/clk/hisilicon/clk-hi3670.c 0x60, 6, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 794 drivers/clk/hisilicon/clk-hi3670.c 0x64, 6, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 797 drivers/clk/hisilicon/clk-hi3670.c 0x88, 0, 4, CLK_MUX_HIWORD_MASK, }, CLK_MUX_HIWORD_MASK 155 drivers/clk/hisilicon/clk-hi6220.c { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 156 drivers/clk/hisilicon/clk-hi6220.c { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 157 drivers/clk/hisilicon/clk-hi6220.c { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 158 drivers/clk/hisilicon/clk-hi6220.c { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 159 drivers/clk/hisilicon/clk-hi6220.c { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 160 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 161 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 162 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 163 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 164 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 165 drivers/clk/hisilicon/clk-hi6220.c { HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1_p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,}, CLK_MUX_HIWORD_MASK 44 drivers/clk/rockchip/clk-muxgrf.c if (mux->flags & CLK_MUX_HIWORD_MASK) CLK_MUX_HIWORD_MASK 876 drivers/clk/rockchip/clk-pll.c pll_mux->flags |= CLK_MUX_HIWORD_MASK; CLK_MUX_HIWORD_MASK 199 drivers/clk/rockchip/clk-px30.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 143 drivers/clk/rockchip/clk-rk3036.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 168 drivers/clk/rockchip/clk-rk3128.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 235 drivers/clk/rockchip/clk-rk3188.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 178 drivers/clk/rockchip/clk-rk3228.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 239 drivers/clk/rockchip/clk-rk3288.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 194 drivers/clk/rockchip/clk-rk3308.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 231 drivers/clk/rockchip/clk-rk3328.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 151 drivers/clk/rockchip/clk-rk3368.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 238 drivers/clk/rockchip/clk-rk3399.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 161 drivers/clk/rockchip/clk-rv1108.c #define MFLAGS CLK_MUX_HIWORD_MASK CLK_MUX_HIWORD_MASK 81 drivers/clk/ti/mux.c if (mux->flags & CLK_MUX_HIWORD_MASK) {