hw_data 4288 drivers/clk/clk.c struct clk_hw_onecell_data *hw_data = data; hw_data 4291 drivers/clk/clk.c if (idx >= hw_data->num) { hw_data 4296 drivers/clk/clk.c return hw_data->hws[idx]; hw_data 319 drivers/clk/meson/axg-aoclk.c .hw_data = &axg_aoclk_onecell_data, hw_data 454 drivers/clk/meson/g12a-aoclk.c .hw_data = &g12a_aoclk_onecell_data, hw_data 280 drivers/clk/meson/gxbb-aoclk.c .hw_data = &gxbb_aoclk_onecell_data, hw_data 73 drivers/clk/meson/meson-aoclk.c for (clkid = 0; clkid < data->hw_data->num; clkid++) { hw_data 74 drivers/clk/meson/meson-aoclk.c if (!data->hw_data->hws[clkid]) hw_data 77 drivers/clk/meson/meson-aoclk.c ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]); hw_data 85 drivers/clk/meson/meson-aoclk.c (void *) data->hw_data); hw_data 27 drivers/clk/meson/meson-aoclk.h const struct clk_hw_onecell_data *hw_data; hw_data 58 drivers/clk/mvebu/armada-37xx-periph.c struct clk_hw_onecell_data *hw_data; hw_data 739 drivers/clk/mvebu/armada-37xx-periph.c driver_data->hw_data = devm_kzalloc(dev, hw_data 740 drivers/clk/mvebu/armada-37xx-periph.c struct_size(driver_data->hw_data, hw_data 743 drivers/clk/mvebu/armada-37xx-periph.c if (!driver_data->hw_data) hw_data 745 drivers/clk/mvebu/armada-37xx-periph.c driver_data->hw_data->num = num_periph; hw_data 755 drivers/clk/mvebu/armada-37xx-periph.c struct clk_hw **hw = &driver_data->hw_data->hws[i]; hw_data 763 drivers/clk/mvebu/armada-37xx-periph.c driver_data->hw_data); hw_data 766 drivers/clk/mvebu/armada-37xx-periph.c clk_hw_unregister(driver_data->hw_data->hws[i]); hw_data 777 drivers/clk/mvebu/armada-37xx-periph.c struct clk_hw_onecell_data *hw_data = data->hw_data; hw_data 782 drivers/clk/mvebu/armada-37xx-periph.c for (i = 0; i < hw_data->num; i++) hw_data 783 drivers/clk/mvebu/armada-37xx-periph.c clk_hw_unregister(hw_data->hws[i]); hw_data 45 drivers/clk/uniphier/clk-uniphier-core.c struct clk_hw_onecell_data *hw_data; hw_data 67 drivers/clk/uniphier/clk-uniphier-core.c hw_data = devm_kzalloc(dev, hw_data 68 drivers/clk/uniphier/clk-uniphier-core.c sizeof(*hw_data) + clk_num * sizeof(struct clk_hw *), hw_data 70 drivers/clk/uniphier/clk-uniphier-core.c if (!hw_data) hw_data 73 drivers/clk/uniphier/clk-uniphier-core.c hw_data->num = clk_num; hw_data 77 drivers/clk/uniphier/clk-uniphier-core.c hw_data->hws[clk_num] = ERR_PTR(-EINVAL); hw_data 88 drivers/clk/uniphier/clk-uniphier-core.c hw_data->hws[p->idx] = hw; hw_data 92 drivers/clk/uniphier/clk-uniphier-core.c hw_data); hw_data 198 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) hw_data 200 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->dev_class = &c3xxx_class; hw_data 201 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->instance_id = c3xxx_class.instances++; hw_data 202 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS; hw_data 203 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS; hw_data 204 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->num_logical_accel = 1; hw_data 205 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES; hw_data 206 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->tx_rx_gap = ADF_C3XXX_RX_RINGS_OFFSET; hw_data 207 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->tx_rings_mask = ADF_C3XXX_TX_RINGS_MASK; hw_data 208 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->alloc_irq = adf_isr_resource_alloc; hw_data 209 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->free_irq = adf_isr_resource_free; hw_data 210 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->enable_error_correction = adf_enable_error_correction; hw_data 211 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 212 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 213 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 214 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 215 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_sram_bar_id = get_sram_bar_id; hw_data 216 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 217 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 218 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 219 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 220 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_sku = get_sku; hw_data 221 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->fw_name = ADF_C3XXX_FW; hw_data 222 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->fw_mmp_name = ADF_C3XXX_MMP; hw_data 223 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->init_admin_comms = adf_init_admin_comms; hw_data 224 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->exit_admin_comms = adf_exit_admin_comms; hw_data 225 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->disable_iov = adf_disable_sriov; hw_data 226 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->send_admin_init = adf_send_admin_init; hw_data 227 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->init_arb = adf_init_arb; hw_data 228 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->exit_arb = adf_exit_arb; hw_data 229 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->get_arb_mapping = adf_get_arbiter_mapping; hw_data 230 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->enable_ints = adf_enable_ints; hw_data 231 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms; hw_data 232 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->reset_device = adf_reset_flr; hw_data 233 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 236 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data) hw_data 238 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c hw_data->dev_class->instances--; hw_data 81 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data); hw_data 82 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data); hw_data 123 drivers/crypto/qat/qat_c3xxx/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 164 drivers/crypto/qat/qat_c3xxx/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 166 drivers/crypto/qat/qat_c3xxx/adf_drv.c if (!hw_data) { hw_data 171 drivers/crypto/qat/qat_c3xxx/adf_drv.c accel_dev->hw_device = hw_data; hw_data 175 drivers/crypto/qat/qat_c3xxx/adf_drv.c &hw_data->fuses); hw_data 178 drivers/crypto/qat/qat_c3xxx/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 179 drivers/crypto/qat/qat_c3xxx/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 180 drivers/crypto/qat/qat_c3xxx/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 182 drivers/crypto/qat/qat_c3xxx/adf_drv.c if (!hw_data->accel_mask || !hw_data->ae_mask || hw_data 183 drivers/crypto/qat/qat_c3xxx/adf_drv.c ((~hw_data->ae_mask) & 0x01)) { hw_data 191 drivers/crypto/qat/qat_c3xxx/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 229 drivers/crypto/qat/qat_c3xxx/adf_drv.c &hw_data->accel_capabilities_mask); hw_data 112 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data) hw_data 114 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->dev_class = &c3xxxiov_class; hw_data 115 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS; hw_data 116 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS; hw_data 117 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->num_logical_accel = 1; hw_data 118 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES; hw_data 119 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET; hw_data 120 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK; hw_data 121 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->alloc_irq = adf_vf_isr_resource_alloc; hw_data 122 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->free_irq = adf_vf_isr_resource_free; hw_data 123 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->enable_error_correction = adf_vf_void_noop; hw_data 124 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->init_admin_comms = adf_vf_int_noop; hw_data 125 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->exit_admin_comms = adf_vf_void_noop; hw_data 126 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->send_admin_init = adf_vf2pf_init; hw_data 127 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->init_arb = adf_vf_int_noop; hw_data 128 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->exit_arb = adf_vf_void_noop; hw_data 129 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->disable_iov = adf_vf2pf_shutdown; hw_data 130 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 131 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 132 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 133 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 134 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 135 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 136 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 137 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 138 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->get_sku = get_sku; hw_data 139 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->enable_ints = adf_vf_void_noop; hw_data 140 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->enable_vf2pf_comms = adf_enable_vf2pf_comms; hw_data 141 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 142 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->dev_class->instances++; hw_data 143 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 146 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data) hw_data 148 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c hw_data->dev_class->instances--; hw_data 149 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 62 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.h void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data); hw_data 63 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.h void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data); hw_data 125 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 159 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 161 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c if (!hw_data) { hw_data 165 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c accel_dev->hw_device = hw_data; hw_data 169 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 170 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 171 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 175 drivers/crypto/qat/qat_c3xxxvf/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 208 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data) hw_data 210 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->dev_class = &c62x_class; hw_data 211 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->instance_id = c62x_class.instances++; hw_data 212 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS; hw_data 213 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS; hw_data 214 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->num_logical_accel = 1; hw_data 215 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES; hw_data 216 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->tx_rx_gap = ADF_C62X_RX_RINGS_OFFSET; hw_data 217 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->tx_rings_mask = ADF_C62X_TX_RINGS_MASK; hw_data 218 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->alloc_irq = adf_isr_resource_alloc; hw_data 219 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->free_irq = adf_isr_resource_free; hw_data 220 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->enable_error_correction = adf_enable_error_correction; hw_data 221 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 222 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 223 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 224 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 225 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_sram_bar_id = get_sram_bar_id; hw_data 226 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 227 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 228 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 229 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 230 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_sku = get_sku; hw_data 231 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->fw_name = ADF_C62X_FW; hw_data 232 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->fw_mmp_name = ADF_C62X_MMP; hw_data 233 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->init_admin_comms = adf_init_admin_comms; hw_data 234 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->exit_admin_comms = adf_exit_admin_comms; hw_data 235 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->disable_iov = adf_disable_sriov; hw_data 236 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->send_admin_init = adf_send_admin_init; hw_data 237 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->init_arb = adf_init_arb; hw_data 238 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->exit_arb = adf_exit_arb; hw_data 239 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->get_arb_mapping = adf_get_arbiter_mapping; hw_data 240 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->enable_ints = adf_enable_ints; hw_data 241 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms; hw_data 242 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->reset_device = adf_reset_flr; hw_data 243 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 246 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data) hw_data 248 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c hw_data->dev_class->instances--; hw_data 82 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data); hw_data 83 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data); hw_data 123 drivers/crypto/qat/qat_c62x/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 164 drivers/crypto/qat/qat_c62x/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 166 drivers/crypto/qat/qat_c62x/adf_drv.c if (!hw_data) { hw_data 171 drivers/crypto/qat/qat_c62x/adf_drv.c accel_dev->hw_device = hw_data; hw_data 175 drivers/crypto/qat/qat_c62x/adf_drv.c &hw_data->fuses); hw_data 178 drivers/crypto/qat/qat_c62x/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 179 drivers/crypto/qat/qat_c62x/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 180 drivers/crypto/qat/qat_c62x/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 182 drivers/crypto/qat/qat_c62x/adf_drv.c if (!hw_data->accel_mask || !hw_data->ae_mask || hw_data 183 drivers/crypto/qat/qat_c62x/adf_drv.c ((~hw_data->ae_mask) & 0x01)) { hw_data 191 drivers/crypto/qat/qat_c62x/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 229 drivers/crypto/qat/qat_c62x/adf_drv.c &hw_data->accel_capabilities_mask); hw_data 232 drivers/crypto/qat/qat_c62x/adf_drv.c i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; hw_data 112 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data) hw_data 114 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->dev_class = &c62xiov_class; hw_data 115 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS; hw_data 116 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS; hw_data 117 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->num_logical_accel = 1; hw_data 118 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES; hw_data 119 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET; hw_data 120 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK; hw_data 121 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->alloc_irq = adf_vf_isr_resource_alloc; hw_data 122 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->free_irq = adf_vf_isr_resource_free; hw_data 123 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->enable_error_correction = adf_vf_void_noop; hw_data 124 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->init_admin_comms = adf_vf_int_noop; hw_data 125 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->exit_admin_comms = adf_vf_void_noop; hw_data 126 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->send_admin_init = adf_vf2pf_init; hw_data 127 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->init_arb = adf_vf_int_noop; hw_data 128 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->exit_arb = adf_vf_void_noop; hw_data 129 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->disable_iov = adf_vf2pf_shutdown; hw_data 130 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 131 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 132 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 133 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 134 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 135 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 136 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 137 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 138 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->get_sku = get_sku; hw_data 139 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->enable_ints = adf_vf_void_noop; hw_data 140 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->enable_vf2pf_comms = adf_enable_vf2pf_comms; hw_data 141 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 142 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->dev_class->instances++; hw_data 143 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 146 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data) hw_data 148 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c hw_data->dev_class->instances--; hw_data 149 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 62 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.h void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data); hw_data 63 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.h void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data); hw_data 125 drivers/crypto/qat/qat_c62xvf/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 159 drivers/crypto/qat/qat_c62xvf/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 161 drivers/crypto/qat/qat_c62xvf/adf_drv.c if (!hw_data) { hw_data 165 drivers/crypto/qat/qat_c62xvf/adf_drv.c accel_dev->hw_device = hw_data; hw_data 169 drivers/crypto/qat/qat_c62xvf/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 170 drivers/crypto/qat/qat_c62xvf/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 171 drivers/crypto/qat/qat_c62xvf/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 175 drivers/crypto/qat/qat_c62xvf/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 120 drivers/crypto/qat/qat_common/adf_accel_engine.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 123 drivers/crypto/qat/qat_common/adf_accel_engine.c if (!hw_data->fw_name) hw_data 127 drivers/crypto/qat/qat_common/adf_accel_engine.c if (hw_data->ae_mask & (1 << ae)) { hw_data 141 drivers/crypto/qat/qat_common/adf_accel_engine.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 144 drivers/crypto/qat/qat_common/adf_accel_engine.c if (!hw_data->fw_name) hw_data 148 drivers/crypto/qat/qat_common/adf_accel_engine.c if (hw_data->ae_mask & (1 << ae)) { hw_data 235 drivers/crypto/qat/qat_common/adf_admin.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 237 drivers/crypto/qat/qat_common/adf_admin.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 113 drivers/crypto/qat/qat_common/adf_common_drv.h void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data); hw_data 389 drivers/crypto/qat/qat_common/adf_ctl_drv.c struct adf_hw_device_data *hw_data; hw_data 403 drivers/crypto/qat/qat_common/adf_ctl_drv.c hw_data = accel_dev->hw_device; hw_data 405 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.num_ae = hw_data->get_num_aes(hw_data); hw_data 406 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.num_accel = hw_data->get_num_accels(hw_data); hw_data 407 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.num_logical_accel = hw_data->num_logical_accel; hw_data 408 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.banks_per_accel = hw_data->num_banks hw_data 409 drivers/crypto/qat/qat_common/adf_ctl_drv.c / hw_data->num_logical_accel; hw_data 410 drivers/crypto/qat/qat_common/adf_ctl_drv.c strlcpy(dev_info.name, hw_data->dev_class->name, sizeof(dev_info.name)); hw_data 411 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.instance_id = hw_data->instance_id; hw_data 412 drivers/crypto/qat/qat_common/adf_ctl_drv.c dev_info.type = hw_data->dev_class->type; hw_data 141 drivers/crypto/qat/qat_common/adf_dev_mgr.c void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data) hw_data 143 drivers/crypto/qat/qat_common/adf_dev_mgr.c struct adf_hw_device_class *class = hw_data->dev_class; hw_data 81 drivers/crypto/qat/qat_common/adf_hw_arbiter.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 93 drivers/crypto/qat/qat_common/adf_hw_arbiter.c for (i = 0; i < hw_data->num_engines; i++) hw_data 97 drivers/crypto/qat/qat_common/adf_hw_arbiter.c hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg); hw_data 102 drivers/crypto/qat/qat_common/adf_hw_arbiter.c for (i = 0; i < hw_data->num_engines; i++) hw_data 118 drivers/crypto/qat/qat_common/adf_hw_arbiter.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 132 drivers/crypto/qat/qat_common/adf_hw_arbiter.c for (i = 0; i < hw_data->num_engines; i++) hw_data 136 drivers/crypto/qat/qat_common/adf_hw_arbiter.c for (i = 0; i < hw_data->num_engines; i++) hw_data 107 drivers/crypto/qat/qat_common/adf_init.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 109 drivers/crypto/qat/qat_common/adf_init.c if (!hw_data) { hw_data 125 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->init_admin_comms && hw_data->init_admin_comms(accel_dev)) { hw_data 130 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->init_arb && hw_data->init_arb(accel_dev)) { hw_data 135 drivers/crypto/qat/qat_common/adf_init.c hw_data->enable_ints(accel_dev); hw_data 151 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->alloc_irq(accel_dev)) { hw_data 173 drivers/crypto/qat/qat_common/adf_init.c hw_data->enable_error_correction(accel_dev); hw_data 174 drivers/crypto/qat/qat_common/adf_init.c hw_data->enable_vf2pf_comms(accel_dev); hw_data 192 drivers/crypto/qat/qat_common/adf_init.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 204 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->send_admin_init(accel_dev)) { hw_data 298 drivers/crypto/qat/qat_common/adf_init.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 302 drivers/crypto/qat/qat_common/adf_init.c if (!hw_data) { hw_data 334 drivers/crypto/qat/qat_common/adf_init.c hw_data->disable_iov(accel_dev); hw_data 337 drivers/crypto/qat/qat_common/adf_init.c hw_data->free_irq(accel_dev); hw_data 345 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->exit_arb) hw_data 346 drivers/crypto/qat/qat_common/adf_init.c hw_data->exit_arb(accel_dev); hw_data 348 drivers/crypto/qat/qat_common/adf_init.c if (hw_data->exit_admin_comms) hw_data 349 drivers/crypto/qat/qat_common/adf_init.c hw_data->exit_admin_comms(accel_dev); hw_data 65 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 72 drivers/crypto/qat/qat_common/adf_isr.c msix_num_entries += hw_data->num_banks; hw_data 77 drivers/crypto/qat/qat_common/adf_isr.c hw_data->num_banks; hw_data 110 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 112 drivers/crypto/qat/qat_common/adf_isr.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 166 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 174 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { hw_data 190 drivers/crypto/qat/qat_common/adf_isr.c cpu = ((accel_dev->accel_id * hw_data->num_banks) + hw_data 214 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 220 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { hw_data 234 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 239 drivers/crypto/qat/qat_common/adf_isr.c msix_num_entries += hw_data->num_banks; hw_data 282 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 285 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) hw_data 295 drivers/crypto/qat/qat_common/adf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 298 drivers/crypto/qat/qat_common/adf_isr.c for (i = 0; i < hw_data->num_banks; i++) { hw_data 62 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 64 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr; hw_data 66 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x0); hw_data 72 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 74 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr; hw_data 76 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x2); hw_data 82 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 84 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 105 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 107 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 129 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 131 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)].virt_addr; hw_data 140 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c pf2vf_offset = hw_data->get_pf2vf_offset(0); hw_data 148 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c pf2vf_offset = hw_data->get_pf2vf_offset(vf_nr); hw_data 239 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 240 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c int bar_id = hw_data->get_misc_bar_id(hw_data); hw_data 246 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr)); hw_data 250 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); hw_data 271 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (vf_compat_ver < hw_data->min_iov_compat_ver) { hw_data 355 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 386 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c if (accel_dev->vf.pf_version >= hw_data->min_iov_compat_ver) hw_data 114 drivers/crypto/qat/qat_common/adf_sriov.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 116 drivers/crypto/qat/qat_common/adf_sriov.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 173 drivers/crypto/qat/qat_common/adf_sriov.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 175 drivers/crypto/qat/qat_common/adf_sriov.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 182 drivers/crypto/qat/qat_common/adf_transport.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 203 drivers/crypto/qat/qat_common/adf_transport.c if (hw_data->tx_rings_mask & (1 << ring->ring_number)) hw_data 389 drivers/crypto/qat/qat_common/adf_transport.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 414 drivers/crypto/qat/qat_common/adf_transport.c if (hw_data->tx_rings_mask & (1 << i)) { hw_data 422 drivers/crypto/qat/qat_common/adf_transport.c if (i < hw_data->tx_rx_gap) { hw_data 427 drivers/crypto/qat/qat_common/adf_transport.c tx_ring = &bank->rings[i - hw_data->tx_rx_gap]; hw_data 443 drivers/crypto/qat/qat_common/adf_transport.c if (hw_data->tx_rings_mask & (1 << i)) hw_data 462 drivers/crypto/qat/qat_common/adf_transport.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 483 drivers/crypto/qat/qat_common/adf_transport.c i = hw_data->get_etr_bar_id(hw_data); hw_data 515 drivers/crypto/qat/qat_common/adf_transport.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 521 drivers/crypto/qat/qat_common/adf_transport.c if (hw_data->tx_rings_mask & (1 << i)) hw_data 118 drivers/crypto/qat/qat_common/adf_vf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 120 drivers/crypto/qat/qat_common/adf_vf_isr.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 125 drivers/crypto/qat/qat_common/adf_vf_isr.c msg = ADF_CSR_RD(pmisc_bar_addr, hw_data->get_pf2vf_offset(0)); hw_data 152 drivers/crypto/qat/qat_common/adf_vf_isr.c ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); hw_data 172 drivers/crypto/qat/qat_common/adf_vf_isr.c ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); hw_data 202 drivers/crypto/qat/qat_common/adf_vf_isr.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 204 drivers/crypto/qat/qat_common/adf_vf_isr.c &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; hw_data 697 drivers/crypto/qat/qat_common/qat_hal.c struct adf_hw_device_data *hw_data = accel_dev->hw_device; hw_data 699 drivers/crypto/qat/qat_common/qat_hal.c &pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)]; hw_data 721 drivers/crypto/qat/qat_common/qat_hal.c &pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)]; hw_data 730 drivers/crypto/qat/qat_common/qat_hal.c handle->hal_handle->ae_mask = hw_data->ae_mask; hw_data 731 drivers/crypto/qat/qat_common/qat_hal.c handle->hal_handle->slice_mask = hw_data->accel_mask; hw_data 736 drivers/crypto/qat/qat_common/qat_hal.c if (!(hw_data->ae_mask & (1 << ae))) hw_data 221 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data) hw_data 223 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->dev_class = &dh895xcc_class; hw_data 224 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->instance_id = dh895xcc_class.instances++; hw_data 225 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->num_banks = ADF_DH895XCC_ETR_MAX_BANKS; hw_data 226 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->num_accel = ADF_DH895XCC_MAX_ACCELERATORS; hw_data 227 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->num_logical_accel = 1; hw_data 228 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES; hw_data 229 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->tx_rx_gap = ADF_DH895XCC_RX_RINGS_OFFSET; hw_data 230 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->tx_rings_mask = ADF_DH895XCC_TX_RINGS_MASK; hw_data 231 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->alloc_irq = adf_isr_resource_alloc; hw_data 232 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->free_irq = adf_isr_resource_free; hw_data 233 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->enable_error_correction = adf_enable_error_correction; hw_data 234 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 235 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 236 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 237 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 238 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 239 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 240 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 241 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 242 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_sram_bar_id = get_sram_bar_id; hw_data 243 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_sku = get_sku; hw_data 244 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->fw_name = ADF_DH895XCC_FW; hw_data 245 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->fw_mmp_name = ADF_DH895XCC_MMP; hw_data 246 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->init_admin_comms = adf_init_admin_comms; hw_data 247 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->exit_admin_comms = adf_exit_admin_comms; hw_data 248 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->disable_iov = adf_disable_sriov; hw_data 249 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->send_admin_init = adf_send_admin_init; hw_data 250 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->init_arb = adf_init_arb; hw_data 251 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->exit_arb = adf_exit_arb; hw_data 252 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->get_arb_mapping = adf_get_arbiter_mapping; hw_data 253 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->enable_ints = adf_enable_ints; hw_data 254 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms; hw_data 255 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->reset_device = adf_reset_sbr; hw_data 256 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 259 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data) hw_data 261 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c hw_data->dev_class->instances--; hw_data 87 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); hw_data 88 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.h void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); hw_data 123 drivers/crypto/qat/qat_dh895xcc/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 164 drivers/crypto/qat/qat_dh895xcc/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 166 drivers/crypto/qat/qat_dh895xcc/adf_drv.c if (!hw_data) { hw_data 171 drivers/crypto/qat/qat_dh895xcc/adf_drv.c accel_dev->hw_device = hw_data; hw_data 175 drivers/crypto/qat/qat_dh895xcc/adf_drv.c &hw_data->fuses); hw_data 178 drivers/crypto/qat/qat_dh895xcc/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 179 drivers/crypto/qat/qat_dh895xcc/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 180 drivers/crypto/qat/qat_dh895xcc/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 182 drivers/crypto/qat/qat_dh895xcc/adf_drv.c if (!hw_data->accel_mask || !hw_data->ae_mask || hw_data 183 drivers/crypto/qat/qat_dh895xcc/adf_drv.c ((~hw_data->ae_mask) & 0x01)) { hw_data 191 drivers/crypto/qat/qat_dh895xcc/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 231 drivers/crypto/qat/qat_dh895xcc/adf_drv.c &hw_data->accel_capabilities_mask); hw_data 112 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data) hw_data 114 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->dev_class = &dh895xcciov_class; hw_data 115 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->num_banks = ADF_DH895XCCIOV_ETR_MAX_BANKS; hw_data 116 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->num_accel = ADF_DH895XCCIOV_MAX_ACCELERATORS; hw_data 117 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->num_logical_accel = 1; hw_data 118 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES; hw_data 119 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->tx_rx_gap = ADF_DH895XCCIOV_RX_RINGS_OFFSET; hw_data 120 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->tx_rings_mask = ADF_DH895XCCIOV_TX_RINGS_MASK; hw_data 121 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->alloc_irq = adf_vf_isr_resource_alloc; hw_data 122 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->free_irq = adf_vf_isr_resource_free; hw_data 123 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->enable_error_correction = adf_vf_void_noop; hw_data 124 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->init_admin_comms = adf_vf_int_noop; hw_data 125 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->exit_admin_comms = adf_vf_void_noop; hw_data 126 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->send_admin_init = adf_vf2pf_init; hw_data 127 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->init_arb = adf_vf_int_noop; hw_data 128 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->exit_arb = adf_vf_void_noop; hw_data 129 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->disable_iov = adf_vf2pf_shutdown; hw_data 130 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_accel_mask = get_accel_mask; hw_data 131 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_ae_mask = get_ae_mask; hw_data 132 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_num_accels = get_num_accels; hw_data 133 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_num_aes = get_num_aes; hw_data 134 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_etr_bar_id = get_etr_bar_id; hw_data 135 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_misc_bar_id = get_misc_bar_id; hw_data 136 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_pf2vf_offset = get_pf2vf_offset; hw_data 137 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_vintmsk_offset = get_vintmsk_offset; hw_data 138 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->get_sku = get_sku; hw_data 139 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->enable_ints = adf_vf_void_noop; hw_data 140 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->enable_vf2pf_comms = adf_enable_vf2pf_comms; hw_data 141 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION; hw_data 142 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->dev_class->instances++; hw_data 143 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 146 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c void adf_clean_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data) hw_data 148 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c hw_data->dev_class->instances--; hw_data 149 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c adf_devmgr_update_class_index(hw_data); hw_data 62 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.h void adf_init_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data); hw_data 63 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.h void adf_clean_hw_data_dh895xcciov(struct adf_hw_device_data *hw_data); hw_data 125 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c struct adf_hw_device_data *hw_data; hw_data 159 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c hw_data = kzalloc_node(sizeof(*hw_data), GFP_KERNEL, hw_data 161 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c if (!hw_data) { hw_data 165 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c accel_dev->hw_device = hw_data; hw_data 169 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data 170 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data 171 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c accel_pci_dev->sku = hw_data->get_sku(hw_data); hw_data 175 drivers/crypto/qat/qat_dh895xccvf/adf_drv.c ADF_DEVICE_NAME_PREFIX, hw_data->dev_class->name, hw_data 545 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c struct hw_gpio *hw_data; hw_data 575 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c hw_data = FROM_HW_GPIO_PIN(ddc->pin_data->pin); hw_data 578 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0; hw_data 783 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 785 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (hw_data->is_nb_dpm_enabled) { hw_data 850 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 854 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (hw_data->sys_info.nb_dpm_enable) { hw_data 855 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false; hw_data 856 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true; hw_data 912 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 914 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->disp_clk_bypass_pending = false; hw_data 915 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->disp_clk_bypass = false; hw_data 920 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 922 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->is_nb_dpm_enabled = false; hw_data 927 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 929 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cc6_setting_changed = false; hw_data 930 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_pstate_separation_time = 0; hw_data 931 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_cc6_disable = false; hw_data 932 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_pstate_disable = false; hw_data 1414 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 1417 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if (hw_data->cc6_settings.cc6_setting_changed) { hw_data 1419 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cc6_setting_changed = false; hw_data 1421 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c smu8_hw_print_display_cfg(&hw_data->cc6_settings); hw_data 1423 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c data |= (hw_data->cc6_settings.cpu_pstate_separation_time hw_data 1427 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0) hw_data 1430 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0) hw_data 1448 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct smu8_hwmgr *hw_data = hwmgr->backend; hw_data 1451 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_pstate_separation_time || hw_data 1452 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c cc6_disable != hw_data->cc6_settings.cpu_cc6_disable || hw_data 1453 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c pstate_disable != hw_data->cc6_settings.cpu_pstate_disable || hw_data 1454 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) { hw_data 1456 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cc6_setting_changed = true; hw_data 1458 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_pstate_separation_time = hw_data 1460 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_cc6_disable = hw_data 1462 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.cpu_pstate_disable = hw_data 1464 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c hw_data->cc6_settings.nb_pstate_switch_disable = hw_data 979 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 981 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; hw_data 985 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; hw_data 1020 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = hw_data 1033 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && hw_data 1034 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 1038 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && hw_data 1039 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 1044 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 1126 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1128 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; hw_data 1164 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = hw_data 1364 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1370 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { hw_data 1371 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { hw_data 1373 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_table.sclk_table.dpm_levels[i].value, hw_data 1374 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_table.mclk_table.dpm_levels[j].value, hw_data 1377 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); hw_data 1483 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1493 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->vbios_boot_state.sclk_bootup_value) { hw_data 1502 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->vbios_boot_state.mclk_bootup_value) { hw_data 1823 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1835 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control) hw_data 1847 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c if (hw_data->is_memory_gddr5) hw_data 1850 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) { hw_data 1937 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->vr_config = table->VRConfig; hw_data 1988 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { hw_data 863 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 865 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; hw_data 869 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; hw_data 907 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = hw_data 912 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; hw_data 923 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && hw_data 924 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 928 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && hw_data 929 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 934 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & hw_data 1033 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1035 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; hw_data 1065 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = hw_data 1070 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; hw_data 1288 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1296 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { hw_data 1297 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { hw_data 1299 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_table.sclk_table.dpm_levels[i].value, hw_data 1300 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_table.mclk_table.dpm_levels[j].value, hw_data 1407 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1417 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->vbios_boot_state.sclk_bootup_value) { hw_data 1426 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->vbios_boot_state.mclk_bootup_value) { hw_data 1926 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); hw_data 1943 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control) hw_data 1955 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c if (hw_data->is_memory_gddr5) hw_data 1958 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) { hw_data 2040 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1, hw_data 2044 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_table.pcie_speed_table.count; hw_data 2109 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { hw_data 116 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct clk_hw_onecell_data *hw_data; hw_data 616 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data; hw_data 621 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; hw_data 623 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; hw_data 664 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct clk_hw_onecell_data *hw_data; hw_data 670 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c hw_data = devm_kzalloc(dev, sizeof(*hw_data) + hw_data 673 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (!hw_data) hw_data 727 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c hw_data->hws[DSI_BYTE_PLL_CLK] = hw; hw_data 787 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; hw_data 789 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c hw_data->num = NUM_PROVIDED_CLKS; hw_data 790 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->hw_data = hw_data; hw_data 793 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_10nm->hw_data); hw_data 142 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct clk_hw_onecell_data *hw_data; hw_data 884 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data; hw_data 887 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk; hw_data 889 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk; hw_data 954 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct clk_hw_onecell_data *hw_data; hw_data 961 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c hw_data = devm_kzalloc(dev, sizeof(*hw_data) + hw_data 964 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c if (!hw_data) hw_data 997 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c hw_data->hws[DSI_BYTE_PLL_CLK] = hw; hw_data 1024 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c hw_data->hws[DSI_PIXEL_PLL_CLK] = hw; hw_data 1028 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c hw_data->num = NUM_PROVIDED_CLKS; hw_data 1029 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_14nm->hw_data = hw_data; hw_data 1032 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_14nm->hw_data); hw_data 171 drivers/net/ethernet/ti/cpmac.c u32 hw_data; hw_data 382 drivers/net/ethernet/ti/cpmac.c desc->hw_data = (u32)desc->data_mapping; hw_data 566 drivers/net/ethernet/ti/cpmac.c desc->hw_data = (u32)desc->data_mapping; hw_data 959 drivers/net/ethernet/ti/cpmac.c desc->hw_data = (u32)desc->data_mapping; hw_data 3562 drivers/net/wireless/intel/ipw2x00/ipw2100.c } hw_data[] = { hw_data 3804 drivers/net/wireless/intel/ipw2x00/ipw2100.c for (i = 0; i < ARRAY_SIZE(hw_data); i++) { hw_data 3805 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(dev, hw_data[i].addr, &val); hw_data 3807 drivers/net/wireless/intel/ipw2x00/ipw2100.c hw_data[i].name, hw_data[i].addr, val); hw_data 124 drivers/regulator/qcom-rpmh-regulator.c const struct rpmh_vreg_hw_data *hw_data; hw_data 149 drivers/regulator/qcom-rpmh-regulator.c const struct rpmh_vreg_hw_data *hw_data; hw_data 273 drivers/regulator/qcom-rpmh-regulator.c pmic_mode = vreg->hw_data->pmic_mode_map[mode]; hw_data 324 drivers/regulator/qcom-rpmh-regulator.c if (load_uA >= vreg->hw_data->hpm_min_load_uA) hw_data 447 drivers/regulator/qcom-rpmh-regulator.c vreg->hw_data = rpmh_data->hw_data; hw_data 453 drivers/regulator/qcom-rpmh-regulator.c if (rpmh_data->hw_data->n_voltages) { hw_data 454 drivers/regulator/qcom-rpmh-regulator.c vreg->rdesc.linear_ranges = &rpmh_data->hw_data->voltage_range; hw_data 456 drivers/regulator/qcom-rpmh-regulator.c vreg->rdesc.n_voltages = rpmh_data->hw_data->n_voltages; hw_data 464 drivers/regulator/qcom-rpmh-regulator.c vreg->rdesc.ops = vreg->hw_data->ops; hw_data 465 drivers/regulator/qcom-rpmh-regulator.c vreg->rdesc.of_map_mode = vreg->hw_data->of_map_mode; hw_data 471 drivers/regulator/qcom-rpmh-regulator.c if (rpmh_data->hw_data->regulator_type == XOB && hw_data 748 drivers/regulator/qcom-rpmh-regulator.c .hw_data = _hw_data, \ hw_data 40 drivers/video/backlight/apple_bl.c static const struct hw_data *hw_data; hw_data 81 drivers/video/backlight/apple_bl.c static const struct hw_data intel_chipset_data = { hw_data 126 drivers/video/backlight/apple_bl.c static const struct hw_data nvidia_chipset_data = { hw_data 151 drivers/video/backlight/apple_bl.c hw_data = &intel_chipset_data; hw_data 153 drivers/video/backlight/apple_bl.c hw_data = &nvidia_chipset_data; hw_data 157 drivers/video/backlight/apple_bl.c if (!hw_data) { hw_data 164 drivers/video/backlight/apple_bl.c intensity = hw_data->backlight_ops.get_brightness(NULL); hw_data 167 drivers/video/backlight/apple_bl.c hw_data->set_brightness(1); hw_data 168 drivers/video/backlight/apple_bl.c if (!hw_data->backlight_ops.get_brightness(NULL)) hw_data 171 drivers/video/backlight/apple_bl.c hw_data->set_brightness(0); hw_data 174 drivers/video/backlight/apple_bl.c if (!request_region(hw_data->iostart, hw_data->iolen, hw_data 182 drivers/video/backlight/apple_bl.c NULL, NULL, &hw_data->backlight_ops, &props); hw_data 185 drivers/video/backlight/apple_bl.c release_region(hw_data->iostart, hw_data->iolen); hw_data 190 drivers/video/backlight/apple_bl.c hw_data->backlight_ops.get_brightness(apple_backlight_device); hw_data 200 drivers/video/backlight/apple_bl.c release_region(hw_data->iostart, hw_data->iolen); hw_data 201 drivers/video/backlight/apple_bl.c hw_data = NULL; hw_data 17 include/sound/pcm-indirect.h unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */ hw_data 53 include/sound/pcm-indirect.h unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data; hw_data 65 include/sound/pcm-indirect.h rec->hw_data += bytes; hw_data 66 include/sound/pcm-indirect.h if (rec->hw_data == rec->hw_buffer_size) hw_data 67 include/sound/pcm-indirect.h rec->hw_data = 0; hw_data 121 include/sound/pcm-indirect.h size_t hw_to_end = rec->hw_buffer_size - rec->hw_data; hw_data 133 include/sound/pcm-indirect.h rec->hw_data += bytes; hw_data 134 include/sound/pcm-indirect.h if ((int)rec->hw_data == rec->hw_buffer_size) hw_data 135 include/sound/pcm-indirect.h rec->hw_data = 0; hw_data 299 net/core/drop_monitor.c net_dm_hw_reset_per_cpu_data(struct per_cpu_dm_data *hw_data) hw_data 311 net/core/drop_monitor.c mod_timer(&hw_data->send_timer, jiffies + HZ / 10); hw_data 314 net/core/drop_monitor.c spin_lock_irqsave(&hw_data->lock, flags); hw_data 315 net/core/drop_monitor.c swap(hw_data->hw_entries, hw_entries); hw_data 316 net/core/drop_monitor.c spin_unlock_irqrestore(&hw_data->lock, flags); hw_data 407 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 411 net/core/drop_monitor.c hw_data = container_of(work, struct per_cpu_dm_data, dm_alert_work); hw_data 413 net/core/drop_monitor.c hw_entries = net_dm_hw_reset_per_cpu_data(hw_data); hw_data 439 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 443 net/core/drop_monitor.c hw_data = this_cpu_ptr(&dm_hw_cpu_data); hw_data 444 net/core/drop_monitor.c spin_lock_irqsave(&hw_data->lock, flags); hw_data 445 net/core/drop_monitor.c hw_entries = hw_data->hw_entries; hw_data 467 net/core/drop_monitor.c if (!timer_pending(&hw_data->send_timer)) { hw_data 468 net/core/drop_monitor.c hw_data->send_timer.expires = jiffies + dm_delay * HZ; hw_data 469 net/core/drop_monitor.c add_timer(&hw_data->send_timer); hw_data 473 net/core/drop_monitor.c spin_unlock_irqrestore(&hw_data->lock, flags); hw_data 882 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 887 net/core/drop_monitor.c hw_data = container_of(work, struct per_cpu_dm_data, dm_alert_work); hw_data 891 net/core/drop_monitor.c spin_lock_irqsave(&hw_data->drop_queue.lock, flags); hw_data 892 net/core/drop_monitor.c skb_queue_splice_tail_init(&hw_data->drop_queue, &list); hw_data 893 net/core/drop_monitor.c spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags); hw_data 905 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 923 net/core/drop_monitor.c hw_data = this_cpu_ptr(&dm_hw_cpu_data); hw_data 925 net/core/drop_monitor.c spin_lock_irqsave(&hw_data->drop_queue.lock, flags); hw_data 926 net/core/drop_monitor.c if (skb_queue_len(&hw_data->drop_queue) < net_dm_queue_len) hw_data 927 net/core/drop_monitor.c __skb_queue_tail(&hw_data->drop_queue, nskb); hw_data 930 net/core/drop_monitor.c spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags); hw_data 932 net/core/drop_monitor.c schedule_work(&hw_data->dm_alert_work); hw_data 937 net/core/drop_monitor.c spin_unlock_irqrestore(&hw_data->drop_queue.lock, flags); hw_data 938 net/core/drop_monitor.c u64_stats_update_begin(&hw_data->stats.syncp); hw_data 939 net/core/drop_monitor.c hw_data->stats.dropped++; hw_data 940 net/core/drop_monitor.c u64_stats_update_end(&hw_data->stats.syncp); hw_data 992 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu); hw_data 995 net/core/drop_monitor.c INIT_WORK(&hw_data->dm_alert_work, ops->hw_work_item_func); hw_data 996 net/core/drop_monitor.c timer_setup(&hw_data->send_timer, sched_send_work, 0); hw_data 997 net/core/drop_monitor.c hw_entries = net_dm_hw_reset_per_cpu_data(hw_data); hw_data 1023 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu); hw_data 1026 net/core/drop_monitor.c del_timer_sync(&hw_data->send_timer); hw_data 1027 net/core/drop_monitor.c cancel_work_sync(&hw_data->dm_alert_work); hw_data 1028 net/core/drop_monitor.c while ((skb = __skb_dequeue(&hw_data->drop_queue))) { hw_data 1391 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data = &per_cpu(dm_hw_cpu_data, cpu); hw_data 1392 net/core/drop_monitor.c struct net_dm_stats *cpu_stats = &hw_data->stats; hw_data 1618 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 1620 net/core/drop_monitor.c hw_data = &per_cpu(dm_hw_cpu_data, cpu); hw_data 1621 net/core/drop_monitor.c __net_dm_cpu_data_init(hw_data); hw_data 1626 net/core/drop_monitor.c struct per_cpu_dm_data *hw_data; hw_data 1628 net/core/drop_monitor.c hw_data = &per_cpu(dm_hw_cpu_data, cpu); hw_data 1629 net/core/drop_monitor.c kfree(hw_data->hw_entries); hw_data 1630 net/core/drop_monitor.c __net_dm_cpu_data_fini(hw_data); hw_data 104 sound/i2c/cs8427.c char *hw_data = udata ? hw_data 109 sound/i2c/cs8427.c if (!memcmp(hw_data, ndata, count)) hw_data 113 sound/i2c/cs8427.c memcpy(hw_data, ndata, count); hw_data 116 sound/i2c/cs8427.c if (memcmp(hw_data, data, count) == 0) { hw_data 596 sound/mips/hal2.c unsigned char *buf = hal2->dac.buffer + rec->hw_data; hw_data 685 sound/mips/hal2.c unsigned char *buf = hal2->adc.buffer + rec->hw_data; hw_data 869 sound/pci/cs46xx/cs46xx_lib.c memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); hw_data 886 sound/pci/cs46xx/cs46xx_lib.c chip->capt.hw_buf.area + rec->hw_data, bytes); hw_data 1083 sound/pci/rme32.c rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); hw_data 1086 sound/pci/rme32.c rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); hw_data 1140 sound/pci/rme32.c memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, hw_data 1165 sound/pci/rme32.c rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,