hubp_regs          32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	hubp1->hubp_regs->reg
hubp_regs        1257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	const struct dcn_mi_registers *hubp_regs,
hubp_regs        1263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	hubp1->hubp_regs = hubp_regs;
hubp_regs         655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	const struct dcn_mi_registers *hubp_regs;
hubp_regs         734 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	const struct dcn_mi_registers *hubp_regs,
hubp_regs         447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn_mi_registers hubp_regs[] = {
hubp_regs         448 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	hubp_regs(0),
hubp_regs         449 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	hubp_regs(1),
hubp_regs         450 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	hubp_regs(2),
hubp_regs         451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	hubp_regs(3),
hubp_regs         981 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			     &hubp_regs[inst], &hubp_shift, &hubp_mask);
hubp_regs          34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	hubp2->hubp_regs->reg
hubp_regs        1276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	const struct dcn_hubp2_registers *hubp_regs,
hubp_regs        1282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	hubp2->hubp_regs = hubp_regs;
hubp_regs         227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	const struct dcn_hubp2_registers *hubp_regs;
hubp_regs         236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 		const struct dcn_hubp2_registers *hubp_regs,
hubp_regs         785 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn_hubp2_registers hubp_regs[] = {
hubp_regs         786 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(0),
hubp_regs         787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(1),
hubp_regs         788 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(2),
hubp_regs         789 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(3),
hubp_regs         790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(4),
hubp_regs         791 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hubp_regs(5)
hubp_regs        1426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
hubp_regs          31 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	hubp21->hubp_regs->reg
hubp_regs         230 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	const struct dcn_hubp2_registers *hubp_regs,
hubp_regs         236 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 	hubp21->hubp_regs = hubp_regs;
hubp_regs         108 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	const struct dcn_hubp2_registers *hubp_regs;
hubp_regs         117 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	const struct dcn_hubp2_registers *hubp_regs,
hubp_regs         473 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn_hubp2_registers hubp_regs[] = {
hubp_regs         474 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		hubp_regs(0),
hubp_regs         475 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		hubp_regs(1),
hubp_regs         476 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		hubp_regs(2),
hubp_regs         477 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		hubp_regs(3)
hubp_regs        1156 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			&hubp_regs[inst], &hubp_shift, &hubp_mask))