hubp 524 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; hubp 1215 drivers/gpu/drm/amd/display/dc/core/dc_resource.c split_pipe->plane_res.hubp = pool->hubps[i]; hubp 1618 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.hubp = pool->hubps[i]; hubp 1888 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.hubp = pool->hubps[tg_inst]; hubp 348 drivers/gpu/drm/amd/display/dc/core/dc_stream.c (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || hubp 598 drivers/gpu/drm/amd/display/dc/core/dc_stream.c struct hubp *hubp; hubp 618 drivers/gpu/drm/amd/display/dc/core/dc_stream.c hubp = pipe_ctx->plane_res.hubp; hubp 619 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (hubp == NULL) hubp 626 drivers/gpu/drm/amd/display/dc/core/dc_stream.c if (hubp->funcs->dmdata_set_attributes != NULL && hubp 628 drivers/gpu/drm/amd/display/dc/core/dc_stream.c hubp->funcs->dmdata_set_attributes(hubp, attr); hubp 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_set_blank(struct hubp *hubp, bool blank) hubp 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->mpcc_id = 0xf; hubp 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->opp_id = OPP_ID_INVALID; hubp 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static void hubp1_disconnect(struct hubp *hubp) hubp 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) hubp 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static unsigned int hubp1_get_underflow_status(struct hubp *hubp) hubp 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_clear_underflow(struct hubp *hubp) hubp 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) hubp 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_vready_workaround(struct hubp *hubp, hubp 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 344 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->request_address = *address; hubp 511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_dcc_control(struct hubp *hubp, bool enable, hubp 516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 526 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); hubp 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_tiling(hubp, tiling_info, format); hubp 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_size(hubp, format, plane_size, dcc); hubp 538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_rotation(hubp, rotation, horizontal_mirror); hubp 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_pixel_format(hubp, format); hubp 543 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 665 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 674 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_requestor(hubp, rq_regs); hubp 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_program_deadline(hubp, dlg_attr, ttu_attr); hubp 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_vready_workaround(hubp, pipe_dest); hubp 680 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 684 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c bool hubp1_is_flip_pending(struct hubp *hubp) hubp 724 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) hubp 748 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp, hubp 751 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c static void hubp1_set_vm_context0_settings(struct hubp *hubp, hubp 780 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 813 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 817 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 846 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_read_state_common(struct hubp *hubp) hubp 848 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1018 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_read_state(struct hubp *hubp) hubp 1020 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1024 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_read_state_common(hubp); hubp 1092 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 1095 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->curs_attr = *attr; hubp 1124 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct hubp *hubp, hubp 1128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (hubp->curs_attr.address.quad_part == 0) hubp 1171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (src_x_offset + (int)hubp->curs_attr.width <= 0) hubp 1177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (src_y_offset + (int)hubp->curs_attr.height <= 0) hubp 1181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); hubp 1199 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_clk_cntl(struct hubp *hubp, bool enable) hubp 1201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) hubp 1209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c void hubp1_init(struct hubp *hubp) hubp 30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define TO_DCN10_HUBP(hubp)\ hubp 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h container_of(hubp, struct dcn10_hubp, base) hubp 653 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp base; hubp 661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 671 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 680 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 684 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 690 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 699 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_dcc_control(struct hubp *hubp, hubp 705 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 710 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h bool hubp1_is_flip_pending(struct hubp *hubp); hubp 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 717 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct hubp *hubp, hubp 721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_set_blank(struct hubp *hubp, bool blank); hubp 723 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void min_set_viewport(struct hubp *hubp, hubp 727 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_clk_cntl(struct hubp *hubp, bool enable); hubp 728 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); hubp 738 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_read_state(struct hubp *hubp); hubp 739 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_clear_underflow(struct hubp *hubp); hubp 743 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_vready_workaround(struct hubp *hubp, hubp 746 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_init(struct hubp *hubp); hubp 747 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h void hubp1_read_state_common(struct hubp *hubp); hubp 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pool->hubps[i]; hubp 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); hubp 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_read_state(hubp); hubp 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->inst, hubp 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp->funcs->hubp_get_underflow_status(hubp)) { hubp 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_clear_underflow(hubp); hubp 620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = dc->res_pool->hubps[0]; hubp 625 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_blank(hubp, true); hubp 640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = dc->res_pool->hubps[0]; hubp 663 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_hubp_blank_en(hubp, false); hubp 877 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp ; hubp 888 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; hubp 889 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) { hubp 890 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) { hubp 913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; hubp 915 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp != NULL && hubp->funcs->set_hubp_blank_en) hubp 916 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_hubp_blank_en(hubp, true); hubp 926 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; hubp 928 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp != NULL && hubp->funcs->hubp_disable_control) hubp 929 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_disable_control(hubp, true); hubp 936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; hubp 938 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp != NULL && hubp->funcs->hubp_disable_control) hubp 939 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_disable_control(hubp, true); hubp 948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp = pipe_ctx->plane_res.hubp; hubp 950 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp != NULL && hubp->funcs->set_hubp_blank_en) hubp 951 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_hubp_blank_en(hubp, true); hubp 979 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 999 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (hubp->funcs->hubp_disconnect) hubp 1000 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_disconnect(hubp); hubp 1008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp) hubp 1017 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->hwss.hubp_pg_control(hws, hubp->inst, false); hubp 1022 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c "Power gated front end %d\n", hubp->inst); hubp 1031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 1033 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c int opp_id = hubp->opp_id; hubp 1037 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_clk_cntl(hubp, false); hubp 1046 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->power_gated = true; hubp 1051 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp); hubp 1065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) hubp 1127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = dc->res_pool->hubps[i]; hubp 1149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp = hubp; hubp 1152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->mpcc_id = dpp->inst; hubp 1153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = OPP_ID_INVALID; hubp 1154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->power_gated = false; hubp 1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp = NULL; hubp 1375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( hubp 1376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, hubp 1812 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp) hubp 1814 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); hubp 1821 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); hubp 1822 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); hubp 1839 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->inst); hubp 1842 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); hubp 1887 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); hubp 2185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 2234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c mpcc_id = hubp->inst; hubp 2258 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->inst, hubp 2263 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; hubp 2264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->mpcc_id = mpcc_id; hubp 2284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 2320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); hubp 2322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_setup( hubp 2323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp, hubp 2328 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_setup_interdependent( hubp 2329 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp, hubp 2356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->mem_program_viewport( hubp 2357 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp, hubp 2390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->hubp_program_surface_config( hubp 2391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp, hubp 2401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->power_gated = false; hubp 2406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_blank(hubp, false); hubp 2607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c old_pipe_ctx->plane_res.hubp && hubp 2608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) hubp 2641 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( hubp 2642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, hubp 2871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) hubp 2899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); hubp 2903 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_blank(hubp, true); hubp 2931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending( hubp 2932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp); hubp 2957 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 3008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width hubp 3009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c || pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) { hubp 3016 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); hubp 3017 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height); hubp 3024 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes( hubp 3025 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.hubp, attributes); hubp 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp); hubp 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct hubp *hubp = pool->hubps[i]; hubp 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); hubp 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c hubp->funcs->hubp_read_state(hubp); hubp 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c hubp->inst, hubp 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c hubp->inst, hubp 510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct hubp *hubp = pool->hubps[i]; hubp 511 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); hubp 513 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c hubp->funcs->hubp_read_state(hubp); hubp 516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c hubp->funcs->hubp_clear_underflow(hubp); hubp 970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static struct hubp *dcn10_hubp_create( hubp 1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; hubp 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, hubp 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_vready_at_or_After_vsync(struct hubp *hubp, hubp 172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 191 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_vready_at_or_After_vsync(hubp, pipe_dest); hubp 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_requestor(hubp, rq_regs); hubp 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_deadline(hubp, dlg_attr, ttu_attr); hubp 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 399 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_dcc_control(struct hubp *hubp, bool enable, hubp 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 414 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 528 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); hubp 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_size(hubp, format, plane_size, dcc); hubp 531 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_rotation(hubp, rotation, horizontal_mirror); hubp 532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_program_pixel_format(hubp, format); hubp 572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->curs_attr = *attr; hubp 605 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); hubp 656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c bool hubp2_dmdata_status_done(struct hubp *hubp) hubp 671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 682 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 846 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->request_address = *address; hubp 852 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 855 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 868 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp) hubp 870 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 878 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) hubp 880 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 885 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c bool hubp2_is_flip_pending(struct hubp *hubp) hubp 888 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 903 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) hubp 909 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_set_blank(struct hubp *hubp, bool blank) hubp 911 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 933 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->mpcc_id = 0xf; hubp 934 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->opp_id = OPP_ID_INVALID; hubp 939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct hubp *hubp, hubp 943 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 948 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c int cursor_height = (int)hubp->curs_attr.height; hubp 949 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c int cursor_width = (int)hubp->curs_attr.width; hubp 960 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (hubp->curs_attr.address.quad_part == 0) hubp 1004 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); hubp 1022 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_clk_cntl(struct hubp *hubp, bool enable) hubp 1024 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 1030 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) hubp 1032 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 1037 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_clear_underflow(struct hubp *hubp) hubp 1039 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 1044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_read_state_common(struct hubp *hubp) hubp 1046 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 1216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c void hubp2_read_state(struct hubp *hubp) hubp 1218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); hubp 1222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_read_state_common(hubp); hubp 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h #define TO_DCN20_HUBP(hubp)\ hubp 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h container_of(hubp, struct dcn20_hubp, base) hubp 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp base; hubp 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_vready_at_or_After_vsync(struct hubp *hubp, hubp 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, hubp 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h bool hubp2_dmdata_status_done(struct hubp *hubp); hubp 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp); hubp 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable); hubp 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_dcc_control(struct hubp *hubp, bool enable, hubp 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 308 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h bool hubp2_is_flip_pending(struct hubp *hubp); hubp 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_set_blank(struct hubp *hubp, bool blank); hubp 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct hubp *hubp, hubp 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_clk_cntl(struct hubp *hubp, bool enable); hubp 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); hubp 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_clear_underflow(struct hubp *hubp); hubp 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_read_state_common(struct hubp *hubp); hubp 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h void hubp2_read_state(struct hubp *hubp); hubp 186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { hubp 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( hubp 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, hubp 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->funcs->hubp_clk_cntl(hubp, false); hubp 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->power_gated = true; hubp 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp); hubp 514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) hubp 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; hubp 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int mpcc_id = pipe_ctx->plane_res.hubp->inst; hubp 917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); hubp 921 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); hubp 936 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); hubp 939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); hubp 992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); hubp 1110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) hubp 1117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) hubp 1205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c old_pipe_ctx->plane_res.hubp && hubp 1206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID) hubp 1239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent( hubp 1240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, hubp 1264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) { hubp 1344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_setup( hubp 1345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, hubp 1421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 1423 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!hubp) hubp 1425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c return hubp->funcs->dmdata_status_done(hubp); hubp 1465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 1479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->funcs->dmdata_set_attributes(hubp, &attr); hubp 1566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); hubp 1568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( hubp 1569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, hubp 1726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 1771 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c mpcc_id = hubp->inst; hubp 1795 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->inst, hubp 1799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = pipe_ctx->stream_res.opp->inst; hubp 1800 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->mpcc_id = mpcc_id; hubp 1915 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) hubp 1916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( hubp 1917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp, flip_immediate); hubp 1970 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = pipe_ctx->plane_res.hubp; hubp 1983 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (!hubp) hubp 1990 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->inst, mode); hubp 2058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubp *hubp = dc->res_pool->hubps[i]; hubp 2064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp = hubp; hubp 2067 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->mpcc_id = dpp->inst; hubp 2068 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->opp_id = OPP_ID_INVALID; hubp 2069 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->power_gated = false; hubp 2072 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubp->funcs->hubp_init(hubp); hubp 2099 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->plane_res.hubp = NULL; hubp 1415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct hubp *dcn20_hubp_create( hubp 1734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; hubp 1814 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; hubp 2953 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; hubp 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct hubp *dcn20_hubp_create( hubp 72 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct hubp *hubp, hubp 75 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); hubp 107 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct hubp *hubp, hubp 111 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp2_program_deadline(hubp, dlg_attr, ttu_attr); hubp 113 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); hubp 117 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct hubp *hubp, hubp 120 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); hubp 149 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct hubp *hubp, hubp 159 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp2_vready_at_or_After_vsync(hubp, pipe_dest); hubp 160 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21_program_requestor(hubp, rq_regs); hubp 161 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21_program_deadline(hubp, dlg_attr, ttu_attr); hubp 165 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c void hubp21_set_vm_system_aperture_settings(struct hubp *hubp, hubp 168 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); hubp 192 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c void hubp21_init(struct hubp *hubp) hubp 197 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); hubp 32 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h #define TO_DCN21_HUBP(hubp)\ hubp 33 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h container_of(hubp, struct dcn21_hubp, base) hubp 106 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct hubp base; hubp 122 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct hubp *hubp, hubp 126 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct hubp *hubp, hubp 131 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h struct hubp *hubp, hubp 1145 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static struct hubp *dcn21_hubp_create( hubp 166 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct hubp *hubps[MAX_PIPES]; hubp 259 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct hubp *hubp; hubp 70 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 77 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 81 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*dcc_control)(struct hubp *hubp, bool enable, hubp 85 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 90 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 95 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 101 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 105 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 109 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 118 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h bool (*hubp_is_flip_pending)(struct hubp *hubp); hubp 120 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*set_blank)(struct hubp *hubp, bool blank); hubp 121 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); hubp 124 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 128 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 132 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_disconnect)(struct hubp *hubp); hubp 134 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); hubp 135 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); hubp 136 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_read_state)(struct hubp *hubp); hubp 137 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_clear_underflow)(struct hubp *hubp); hubp 138 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); hubp 139 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); hubp 140 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h void (*hubp_init)(struct hubp *hubp); hubp 144 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 148 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 151 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h bool (*dmdata_status_done)(struct hubp *hubp); hubp 153 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 157 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp); hubp 160 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct hubp *hubp, hubp 82 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct hubp; hubp 291 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h struct hubp *hubp);