hubbub 328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> hubbub 975 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format( hubbub 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_wm_read_state(struct hubbub *hubbub, hubbub 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow) hubbub 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub) hubbub 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub) hubbub 122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_wm_change_req_wa(struct hubbub *hubbub) hubbub 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub, hubbub 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub, hubbub 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 534 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub, hubbub 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 604 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub, hubbub 609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 616 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 623 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); hubbub 633 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct hubbub *hubbub, hubbub 636 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) hubbub 697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_soft_reset(struct hubbub *hubbub, bool reset) hubbub 715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub, hubbub 859 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 952 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c void hubbub1_construct(struct hubbub *hubbub, hubbub 958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); hubbub 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h #define TO_DCN10_HUBBUB(hubbub)\ hubbub 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h container_of(hubbub, struct dcn10_hubbub, base) hubbub 302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub base; hubbub 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub, hubbub 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub); hubbub 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h void hubbub1_wm_change_req_wa(struct hubbub *hubbub); hubbub 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub, hubbub 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); hubbub 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); hubbub 330 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub); hubbub 332 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h void hubbub1_wm_read_state(struct hubbub *hubbub, hubbub 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h void hubbub1_soft_reset(struct hubbub *hubbub, bool reset); hubbub 336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h void hubbub1_construct(struct hubbub *hubbub, hubbub 343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub, hubbub 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub, hubbub 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct hubbub *hubbub, hubbub 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); hubbub 673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) hubbub 675 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub); hubbub 695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) hubbub 697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub)) hubbub 698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true); hubbub 920 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub1_soft_reset(dc->res_pool->hubbub, true); hubbub 943 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub1_soft_reset(dc->res_pool->hubbub, false); hubbub 963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { hubbub 970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) hubbub 1221 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (res_pool->dccg && res_pool->hubbub) { hubbub 1227 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, hubbub 2666 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub1_wm_change_req_wa(dc->res_pool->hubbub); hubbub 2679 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false); hubbub 2689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubbub *hubbub = dc->res_pool->hubbub; hubbub 2704 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub->funcs->program_watermarks(hubbub, hubbub 2721 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubbub *hubbub = dc->res_pool->hubbub; hubbub 2736 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub->funcs->program_watermarks(hubbub, hubbub 2948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub; hubbub 2951 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hubbub->funcs->update_dchub(hubbub, dh_data); hubbub 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); hubbub 700 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) hubbub 901 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubbub != NULL) { hubbub 902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.hubbub); hubbub 903 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubbub = NULL; hubbub 1122 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( hubbub 1123 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dc->res_pool->hubbub, hubbub 1532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.hubbub = dcn10_hubbub_create(ctx); hubbub 1533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.hubbub == NULL) { hubbub 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, hubbub 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dc *dc = hubbub->ctx->dc; hubbub 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (!hubbub->funcs->dcc_support_pixel_format(input->format, hubbub 235 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, hubbub 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c void hubbub2_init_vm_ctx(struct hubbub *hubbub, hubbub 352 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, hubbub 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c void hubbub2_update_dchub(struct hubbub *hubbub, hubbub 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c void hubbub2_wm_read_state(struct hubbub *hubbub, hubbub 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, hubbub 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct hubbub *hubbub, hubbub 568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 573 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 585 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); hubbub 606 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c void hubbub2_construct(struct dcn20_hubbub *hubbub, hubbub 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->base.ctx = ctx; hubbub 614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->base.funcs = &hubbub2_funcs; hubbub 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->regs = hubbub_regs; hubbub 617 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->shifts = hubbub_shift; hubbub 618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->masks = hubbub_mask; hubbub 620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->debug_test_index_pstate = 0xB; hubbub 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h #define TO_DCN20_HUBBUB(hubbub)\ hubbub 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h container_of(hubbub, struct dcn20_hubbub, base) hubbub 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h struct hubbub base; hubbub 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h void hubbub2_construct(struct dcn20_hubbub *hubbub, hubbub 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, hubbub 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h bool hubbub2_initialize_vmids(struct hubbub *hubbub, hubbub 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, hubbub 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h void hubbub2_init_vm_ctx(struct hubbub *hubbub, hubbub 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h void hubbub2_update_dchub(struct hubbub *hubbub, hubbub 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, hubbub 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h void hubbub2_wm_read_state(struct hubbub *hubbub, hubbub 1276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubbub *hubbub = dc->res_pool->hubbub; hubbub 1284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubbub->funcs->program_watermarks(hubbub, hubbub 1294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c struct hubbub *hubbub = dc->res_pool->hubbub; hubbub 1297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hubbub->funcs->program_watermarks(hubbub, hubbub 1506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); hubbub 1524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); hubbub 1091 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) hubbub 1094 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), hubbub 1097 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!hubbub) hubbub 1100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c hubbub2_construct(hubbub, ctx, hubbub 1106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct dcn20_vmid *vmid = &hubbub->vmid[i]; hubbub 1115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return &hubbub->base; hubbub 1326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubbub != NULL) { hubbub 1327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(pool->base.hubbub); hubbub 1328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubbub = NULL; hubbub 2965 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( hubbub 2966 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dc->res_pool->hubbub, hubbub 3690 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.hubbub = dcn20_hubbub_create(ctx); hubbub 3691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.hubbub == NULL) { hubbub 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h struct hubbub *dcn20_hubbub_create(struct dc_context *ctx); hubbub 72 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c void dcn21_dchvm_init(struct hubbub *hubbub) hubbub 74 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 110 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c static int hubbub21_init_dchub(struct hubbub *hubbub, hubbub 113 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 128 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c dcn21_dchvm_init(hubbub); hubbub 134 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct hubbub *hubbub, hubbub 139 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 269 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct hubbub *hubbub, hubbub 274 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 403 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct hubbub *hubbub, hubbub 408 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 477 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct hubbub *hubbub, hubbub 482 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 484 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 485 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 486 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); hubbub 509 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); hubbub 512 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c void hubbub21_wm_read_state(struct hubbub *hubbub, hubbub 515 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); hubbub 590 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c void hubbub21_construct(struct dcn20_hubbub *hubbub, hubbub 596 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->base.ctx = ctx; hubbub 598 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->base.funcs = &hubbub21_funcs; hubbub 600 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->regs = hubbub_regs; hubbub 601 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->shifts = hubbub_shift; hubbub 602 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->masks = hubbub_mask; hubbub 604 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->debug_test_index_pstate = 0xB; hubbub 116 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h void dcn21_dchvm_init(struct hubbub *hubbub); hubbub 118 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h struct hubbub *hubbub, hubbub 123 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h void hubbub21_wm_read_state(struct hubbub *hubbub, hubbub 126 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h void hubbub21_construct(struct dcn20_hubbub *hubbub, hubbub 854 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubbub != NULL) { hubbub 855 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(pool->base.hubbub); hubbub 856 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubbub = NULL; hubbub 1164 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx) hubbub 1168 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), hubbub 1171 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (!hubbub) hubbub 1174 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c hubbub21_construct(hubbub, ctx, hubbub 1180 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct dcn20_vmid *vmid = &hubbub->vmid[i]; hubbub 1189 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return &hubbub->base; hubbub 1620 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.hubbub = dcn21_hubbub_create(ctx); hubbub 1621 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.hubbub == NULL) { hubbub 173 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct hubbub *hubbub; hubbub 107 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h struct hubbub *hubbub, hubbub 112 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h struct hubbub *hubbub, hubbub 115 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h struct hubbub *hubbub, hubbub 120 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h bool (*get_dcc_compression_cap)(struct hubbub *hubbub, hubbub 134 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h void (*wm_read_state)(struct hubbub *hubbub, hubbub 137 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h void (*get_dchub_ref_freq)(struct hubbub *hubbub, hubbub 142 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h struct hubbub *hubbub, hubbub 147 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub); hubbub 148 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);