hs_timing 958 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t hs_timing:1; hs_timing 972 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t hs_timing:1; hs_timing 1113 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t hs_timing:1; hs_timing 1127 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t hs_timing:1; hs_timing 42 drivers/clk/socfpga/clk-gate-a10.c u32 hs_timing; hs_timing 78 drivers/clk/socfpga/clk-gate-a10.c hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); hs_timing 81 drivers/clk/socfpga/clk-gate-a10.c SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); hs_timing 116 drivers/clk/socfpga/clk-gate.c u32 hs_timing; hs_timing 157 drivers/clk/socfpga/clk-gate.c hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); hs_timing 159 drivers/clk/socfpga/clk-gate.c hs_timing); hs_timing 74 drivers/mmc/host/dw_mmc-k3.c static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {