host1x_sync_readl  148 drivers/gpu/host1x/dev.h u32 host1x_sync_readl(struct host1x *host1x, u32 r);
host1x_sync_readl  176 drivers/gpu/host1x/hw/cdma_hw.c 	u32 cmdproc_stop = host1x_sync_readl(host, HOST1X_SYNC_CMDPROC_STOP);
host1x_sync_readl   26 drivers/gpu/host1x/hw/debug_hw_1x01.c 	cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));
host1x_sync_readl   27 drivers/gpu/host1x/hw/debug_hw_1x01.c 	cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));
host1x_sync_readl   48 drivers/gpu/host1x/hw/debug_hw_1x01.c 			host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));
host1x_sync_readl   88 drivers/gpu/host1x/hw/debug_hw_1x01.c 	val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);
host1x_sync_readl   92 drivers/gpu/host1x/hw/debug_hw_1x01.c 	val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));
host1x_sync_readl  102 drivers/gpu/host1x/hw/debug_hw_1x01.c 		val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);
host1x_sync_readl  134 drivers/gpu/host1x/hw/debug_hw_1x01.c 			host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));
host1x_sync_readl   40 drivers/gpu/host1x/hw/intr_hw.c 		reg = host1x_sync_readl(host,
host1x_sync_readl   46 drivers/gpu/host1x/hw/syncpt_hw.c 		host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
host1x_sync_readl   61 drivers/gpu/host1x/hw/syncpt_hw.c 		live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));