host1x_hypervisor_writel 176 drivers/gpu/host1x/dev.c host1x_hypervisor_writel(host, entry->offset, entry->base); host1x_hypervisor_writel 177 drivers/gpu/host1x/dev.c host1x_hypervisor_writel(host, entry->limit, entry->base + 4); host1x_hypervisor_writel 145 drivers/gpu/host1x/dev.h void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v); host1x_hypervisor_writel 221 drivers/gpu/host1x/hw/channel_hw.c host1x_hypervisor_writel( host1x_hypervisor_writel 77 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE); host1x_hypervisor_writel 82 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL); host1x_hypervisor_writel 97 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, val, host1x_hypervisor_writel 123 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL); host1x_hypervisor_writel 124 drivers/gpu/host1x/hw/debug_hw_1x06.c host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE); host1x_hypervisor_writel 131 drivers/gpu/host1x/hw/syncpt_hw.c host1x_hypervisor_writel(host, HOST1X_HV_SYNCPT_PROT_EN_CH_EN,