host1x_debug_cont   37 drivers/gpu/host1x/debug.h void __printf(2, 3) host1x_debug_cont(struct output *o, const char *fmt, ...);
host1x_debug_cont   52 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
host1x_debug_cont   58 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
host1x_debug_cont   63 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "INCR(offset=%03x, [",
host1x_debug_cont   66 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "])\n");
host1x_debug_cont   72 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "NONINCR(offset=%03x, [",
host1x_debug_cont   75 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "])\n");
host1x_debug_cont   81 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [",
host1x_debug_cont   84 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "])\n");
host1x_debug_cont   89 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n",
host1x_debug_cont   94 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4);
host1x_debug_cont   98 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
host1x_debug_cont  105 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
host1x_debug_cont  110 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
host1x_debug_cont  115 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
host1x_debug_cont  120 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "%s(offset=%06x, ",
host1x_debug_cont  125 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "[])\n");
host1x_debug_cont  128 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "unknown)\n");
host1x_debug_cont  131 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "[");
host1x_debug_cont  136 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
host1x_debug_cont  144 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n",
host1x_debug_cont  147 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n",
host1x_debug_cont  150 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val);
host1x_debug_cont  154 drivers/gpu/host1x/hw/debug_hw.c 		host1x_debug_cont(o, "UNKNOWN\n");
host1x_debug_cont  186 drivers/gpu/host1x/hw/debug_hw.c 			host1x_debug_cont(o, "%08x%s", val,
host1x_debug_cont  108 drivers/gpu/host1x/hw/debug_hw_1x01.c 			host1x_debug_cont(o, "%08x%s", val,
host1x_debug_cont  120 drivers/gpu/host1x/hw/debug_hw_1x01.c 		host1x_debug_cont(o, ", ...])\n");
host1x_debug_cont  108 drivers/gpu/host1x/hw/debug_hw_1x06.c 			host1x_debug_cont(o, "%08x%s", val,
host1x_debug_cont  120 drivers/gpu/host1x/hw/debug_hw_1x06.c 		host1x_debug_cont(o, ", ...])\n");