host1x_ch_writel 149 drivers/gpu/host1x/dev.h void host1x_ch_writel(struct host1x_channel *ch, u32 r, u32 v); host1x_ch_writel 55 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, host1x_ch_writel 59 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART); host1x_ch_writel 61 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); host1x_ch_writel 63 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); host1x_ch_writel 65 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMAPUT_HI); host1x_ch_writel 67 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND); host1x_ch_writel 69 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); host1x_ch_writel 73 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | host1x_ch_writel 79 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL); host1x_ch_writel 100 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, host1x_ch_writel 107 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART); host1x_ch_writel 109 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); host1x_ch_writel 111 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND); host1x_ch_writel 113 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); host1x_ch_writel 117 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, getptr, HOST1X_CHANNEL_DMAPUT); host1x_ch_writel 118 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | host1x_ch_writel 130 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, host1x_ch_writel 132 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); host1x_ch_writel 135 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL); host1x_ch_writel 148 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, cdma->push_buffer.pos, host1x_ch_writel 162 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, host1x_ch_writel 174 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, stop ? 0x1 : 0x0, HOST1X_CHANNEL_CMDPROC_STOP); host1x_ch_writel 188 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, 0x1, HOST1X_CHANNEL_TEARDOWN); host1x_ch_writel 217 drivers/gpu/host1x/hw/cdma_hw.c host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, host1x_ch_writel 114 drivers/gpu/host1x/hw/channel_hw.c host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID); host1x_ch_writel 224 drivers/gpu/host1x/hw/channel_hw.c host1x_ch_writel(ch,