host1x_ch_readl   150 drivers/gpu/host1x/dev.h u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);
host1x_ch_readl   125 drivers/gpu/host1x/hw/cdma_hw.c 		host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),
host1x_ch_readl   126 drivers/gpu/host1x/hw/cdma_hw.c 		host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT),
host1x_ch_readl   213 drivers/gpu/host1x/hw/cdma_hw.c 		__func__, host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),
host1x_ch_readl   214 drivers/gpu/host1x/hw/cdma_hw.c 		host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT),
host1x_ch_readl    23 drivers/gpu/host1x/hw/debug_hw_1x01.c 	dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
host1x_ch_readl    24 drivers/gpu/host1x/hw/debug_hw_1x01.c 	dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
host1x_ch_readl    25 drivers/gpu/host1x/hw/debug_hw_1x01.c 	dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
host1x_ch_readl    76 drivers/gpu/host1x/hw/debug_hw_1x01.c 	val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);
host1x_ch_readl    23 drivers/gpu/host1x/hw/debug_hw_1x06.c 	dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
host1x_ch_readl    24 drivers/gpu/host1x/hw/debug_hw_1x06.c 	dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
host1x_ch_readl    25 drivers/gpu/host1x/hw/debug_hw_1x06.c 	dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
host1x_ch_readl    26 drivers/gpu/host1x/hw/debug_hw_1x06.c 	offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);
host1x_ch_readl    27 drivers/gpu/host1x/hw/debug_hw_1x06.c 	class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);
host1x_ch_readl    28 drivers/gpu/host1x/hw/debug_hw_1x06.c 	ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);
host1x_ch_readl    65 drivers/gpu/host1x/hw/debug_hw_1x06.c 	val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
host1x_ch_readl    72 drivers/gpu/host1x/hw/debug_hw_1x06.c 	val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);