hdmiphy_config     85 drivers/gpu/drm/exynos/exynos_hdmi.c 	const struct hdmiphy_config *data;
hdmiphy_config    156 drivers/gpu/drm/exynos/exynos_hdmi.c static const struct hdmiphy_config hdmiphy_v13_configs[] = {
hdmiphy_config    204 drivers/gpu/drm/exynos/exynos_hdmi.c static const struct hdmiphy_config hdmiphy_v14_configs[] = {
hdmiphy_config    369 drivers/gpu/drm/exynos/exynos_hdmi.c static const struct hdmiphy_config hdmiphy_5420_configs[] = {
hdmiphy_config    525 drivers/gpu/drm/exynos/exynos_hdmi.c static const struct hdmiphy_config hdmiphy_5433_configs[] = {
hdmiphy_config     64 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
hdmiphy_config    147 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 		if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
hdmiphy_config    148 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 		    (hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
hdmiphy_config    149 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 			val |= (hdmiphy_config[i].config[0]
hdmiphy_config    153 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 			val = hdmiphy_config[i].config[1];
hdmiphy_config    156 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 			val = hdmiphy_config[i].config[2];
hdmiphy_config    160 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 					 hdmiphy_config[i].config[0],
hdmiphy_config    161 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 					 hdmiphy_config[i].config[1],
hdmiphy_config    162 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c 					 hdmiphy_config[i].config[2]);