hdmi_phy          232 drivers/gpu/drm/mediatek/mtk_hdmi.c 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
hdmi_phy          240 drivers/gpu/drm/mediatek/mtk_hdmi.c 	if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
hdmi_phy           18 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           21 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	void __iomem *reg = hdmi_phy->regs + offset;
hdmi_phy           29 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           32 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	void __iomem *reg = hdmi_phy->regs + offset;
hdmi_phy           40 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           43 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	void __iomem *reg = hdmi_phy->regs + offset;
hdmi_phy           58 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
hdmi_phy           61 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	ret = clk_prepare_enable(hdmi_phy->pll);
hdmi_phy           65 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
hdmi_phy           71 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
hdmi_phy           73 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
hdmi_phy           74 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	clk_disable_unprepare(hdmi_phy->pll);
hdmi_phy           80 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
hdmi_phy           82 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	if (hdmi_phy && hdmi_phy->conf &&
hdmi_phy           83 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	    hdmi_phy->conf->hdmi_phy_enable_tmds &&
hdmi_phy           84 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	    hdmi_phy->conf->hdmi_phy_disable_tmds)
hdmi_phy           87 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
hdmi_phy           91 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
hdmi_phy           94 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	clk_init->flags = hdmi_phy->conf->flags;
hdmi_phy           95 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
hdmi_phy          101 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy;
hdmi_phy          114 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
hdmi_phy          115 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	if (!hdmi_phy)
hdmi_phy          119 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->regs = devm_ioremap_resource(dev, mem);
hdmi_phy          120 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	if (IS_ERR(hdmi_phy->regs)) {
hdmi_phy          121 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 		ret = PTR_ERR(hdmi_phy->regs);
hdmi_phy          142 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->dev = dev;
hdmi_phy          143 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->conf =
hdmi_phy          145 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
hdmi_phy          146 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->pll_hw.init = &clk_init;
hdmi_phy          147 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
hdmi_phy          148 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	if (IS_ERR(hdmi_phy->pll)) {
hdmi_phy          149 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 		ret = PTR_ERR(hdmi_phy->pll);
hdmi_phy          155 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 				   &hdmi_phy->ibias);
hdmi_phy          162 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 				   &hdmi_phy->ibias_up);
hdmi_phy          169 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->drv_imp_clk = 0x30;
hdmi_phy          170 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->drv_imp_d2 = 0x30;
hdmi_phy          171 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->drv_imp_d1 = 0x30;
hdmi_phy          172 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	hdmi_phy->drv_imp_d0 = 0x30;
hdmi_phy          174 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
hdmi_phy          179 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 	phy_set_drvdata(phy, hdmi_phy);
hdmi_phy          188 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c 				   hdmi_phy->pll);
hdmi_phy           26 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h 	void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
hdmi_phy           27 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h 	void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
hdmi_phy           45 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           47 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           49 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
hdmi_phy           70 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy           72 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
hdmi_phy           73 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
hdmi_phy           74 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
hdmi_phy           75 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
hdmi_phy           77 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
hdmi_phy           78 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
hdmi_phy           79 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
hdmi_phy           81 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
hdmi_phy           82 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
hdmi_phy           83 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
hdmi_phy           84 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
hdmi_phy           91 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy           93 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
hdmi_phy           94 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
hdmi_phy           95 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
hdmi_phy           96 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
hdmi_phy           98 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
hdmi_phy           99 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
hdmi_phy          100 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
hdmi_phy          102 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
hdmi_phy          103 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
hdmi_phy          104 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
hdmi_phy          105 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
hdmi_phy          118 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          128 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
hdmi_phy          129 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
hdmi_phy          130 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
hdmi_phy          131 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
hdmi_phy          133 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
hdmi_phy          135 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
hdmi_phy          137 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
hdmi_phy          139 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
hdmi_phy          141 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
hdmi_phy          143 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
hdmi_phy          145 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
hdmi_phy          147 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
hdmi_phy          150 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
hdmi_phy          151 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
hdmi_phy          153 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
hdmi_phy          154 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
hdmi_phy          156 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
hdmi_phy          157 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
hdmi_phy          165 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          168 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	val = (readl(hdmi_phy->regs + HDMI_CON6)
hdmi_phy          182 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	val = (readl(hdmi_phy->regs + HDMI_CON6)
hdmi_phy          185 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	val = (readl(hdmi_phy->regs + HDMI_CON2)
hdmi_phy          189 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
hdmi_phy          203 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
hdmi_phy          205 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
hdmi_phy          206 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
hdmi_phy          207 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
hdmi_phy          208 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
hdmi_phy          210 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
hdmi_phy          211 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
hdmi_phy          212 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
hdmi_phy          214 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
hdmi_phy          215 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
hdmi_phy          216 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
hdmi_phy          217 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
hdmi_phy          221 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
hdmi_phy          223 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
hdmi_phy          224 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
hdmi_phy          225 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
hdmi_phy          226 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
hdmi_phy          228 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
hdmi_phy          229 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
hdmi_phy          230 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
hdmi_phy          232 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
hdmi_phy          233 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
hdmi_phy          234 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
hdmi_phy          235 drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
hdmi_phy          160 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          162 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	dev_dbg(hdmi_phy->dev, "%s\n", __func__);
hdmi_phy          164 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
hdmi_phy          165 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
hdmi_phy          166 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
hdmi_phy          167 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
hdmi_phy          169 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
hdmi_phy          171 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
hdmi_phy          172 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
hdmi_phy          179 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          181 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	dev_dbg(hdmi_phy->dev, "%s\n", __func__);
hdmi_phy          183 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
hdmi_phy          184 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
hdmi_phy          186 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
hdmi_phy          188 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
hdmi_phy          189 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
hdmi_phy          190 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
hdmi_phy          197 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          199 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	hdmi_phy->pll_rate = rate;
hdmi_phy          211 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          218 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
hdmi_phy          232 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
hdmi_phy          234 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
hdmi_phy          235 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
hdmi_phy          238 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
hdmi_phy          240 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
hdmi_phy          243 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
hdmi_phy          245 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
hdmi_phy          251 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
hdmi_phy          255 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 		hdmi_ibias = hdmi_phy->ibias;
hdmi_phy          257 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
hdmi_phy          261 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 		hdmi_ibias = hdmi_phy->ibias_up;
hdmi_phy          263 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
hdmi_phy          272 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
hdmi_phy          275 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
hdmi_phy          276 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
hdmi_phy          277 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
hdmi_phy          278 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
hdmi_phy          279 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
hdmi_phy          282 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
hdmi_phy          297 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
hdmi_phy          299 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	return hdmi_phy->pll_rate;
hdmi_phy          310 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
hdmi_phy          312 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
hdmi_phy          318 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
hdmi_phy          320 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
hdmi_phy           22 drivers/gpu/drm/msm/hdmi/hdmi.h struct hdmi_phy;
hdmi_phy           62 drivers/gpu/drm/msm/hdmi/hdmi.h 	struct hdmi_phy *phy;
hdmi_phy          146 drivers/gpu/drm/msm/hdmi/hdmi.h 	void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
hdmi_phy          147 drivers/gpu/drm/msm/hdmi/hdmi.h 	void (*powerdown)(struct hdmi_phy *phy);
hdmi_phy          168 drivers/gpu/drm/msm/hdmi/hdmi.h static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
hdmi_phy          173 drivers/gpu/drm/msm/hdmi/hdmi.h static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
hdmi_phy          178 drivers/gpu/drm/msm/hdmi/hdmi.h int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
hdmi_phy          179 drivers/gpu/drm/msm/hdmi/hdmi.h void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
hdmi_phy          180 drivers/gpu/drm/msm/hdmi/hdmi.h void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
hdmi_phy          181 drivers/gpu/drm/msm/hdmi/hdmi.h void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
hdmi_phy          148 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 	struct hdmi_phy *phy = hdmi->phy;
hdmi_phy          182 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c 	struct hdmi_phy *phy = hdmi->phy;
hdmi_phy           10 drivers/gpu/drm/msm/hdmi/hdmi_phy.c static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy)
hdmi_phy           57 drivers/gpu/drm/msm/hdmi/hdmi_phy.c int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy)
hdmi_phy           82 drivers/gpu/drm/msm/hdmi/hdmi_phy.c void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy)
hdmi_phy           97 drivers/gpu/drm/msm/hdmi/hdmi_phy.c void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock)
hdmi_phy          105 drivers/gpu/drm/msm/hdmi/hdmi_phy.c void msm_hdmi_phy_powerdown(struct hdmi_phy *phy)
hdmi_phy          141 drivers/gpu/drm/msm/hdmi/hdmi_phy.c 	struct hdmi_phy *phy;
hdmi_phy            9 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c static void hdmi_phy_8960_powerup(struct hdmi_phy *phy,
hdmi_phy           28 drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c static void hdmi_phy_8960_powerdown(struct hdmi_phy *phy)
hdmi_phy           81 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
hdmi_phy          399 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	struct hdmi_phy *phy = pll_get_phy(pll);
hdmi_phy          543 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static int hdmi_8996_phy_ready_status(struct hdmi_phy *phy)
hdmi_phy          595 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	struct hdmi_phy *phy = pll_get_phy(pll);
hdmi_phy          667 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	struct hdmi_phy *phy = pll_get_phy(pll);
hdmi_phy           11 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
hdmi_phy           95 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
hdmi_phy            9 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy,
hdmi_phy           22 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c static void hdmi_phy_8x74_powerdown(struct hdmi_phy *phy)
hdmi_phy          247 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
hdmi_phy          255 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	struct hdmi_phy *phy = pll_get_phy(pll);
hdmi_phy          340 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	struct hdmi_phy *phy = pll_get_phy(pll);