CLK_ENABLE_ON_INIT 10 arch/sh/kernel/cpu/clock-cpg.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 16 arch/sh/kernel/cpu/clock-cpg.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 21 arch/sh/kernel/cpu/clock-cpg.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 26 arch/sh/kernel/cpu/clock-cpg.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 54 arch/sh/kernel/cpu/sh2a/clock-sh7264.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 83 arch/sh/kernel/cpu/sh2a/clock-sh7264.c | CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 50 arch/sh/kernel/cpu/sh2a/clock-sh7269.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 65 arch/sh/kernel/cpu/sh2a/clock-sh7269.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 80 arch/sh/kernel/cpu/sh2a/clock-sh7269.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 111 arch/sh/kernel/cpu/sh2a/clock-sh7269.c | CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 113 arch/sh/kernel/cpu/sh2a/clock-sh7269.c | CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 46 arch/sh/kernel/cpu/sh4/clock-sh4-202.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 61 arch/sh/kernel/cpu/sh4/clock-sh4-202.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 137 arch/sh/kernel/cpu/sh4/clock-sh4-202.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 59 arch/sh/kernel/cpu/sh4a/clock-sh7343.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 78 arch/sh/kernel/cpu/sh4a/clock-sh7343.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 109 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 110 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 111 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 112 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 113 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 139 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 140 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 141 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 142 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 143 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 176 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 180 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 181 arch/sh/kernel/cpu/sh4a/clock-sh7343.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 59 arch/sh/kernel/cpu/sh4a/clock-sh7366.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 81 arch/sh/kernel/cpu/sh4a/clock-sh7366.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 112 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 113 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 114 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 115 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 116 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 142 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 143 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 144 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 145 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 146 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 174 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 178 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 179 arch/sh/kernel/cpu/sh4a/clock-sh7366.c [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 62 arch/sh/kernel/cpu/sh4a/clock-sh7722.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 84 arch/sh/kernel/cpu/sh4a/clock-sh7722.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 114 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 115 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 116 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 117 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 118 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 142 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 143 arch/sh/kernel/cpu/sh4a/clock-sh7722.c [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 63 arch/sh/kernel/cpu/sh4a/clock-sh7723.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 85 arch/sh/kernel/cpu/sh4a/clock-sh7723.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 115 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 116 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 117 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 118 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 119 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 143 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 144 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 145 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 146 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 147 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 148 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 149 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 151 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 178 arch/sh/kernel/cpu/sh4a/clock-sh7723.c [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 68 arch/sh/kernel/cpu/sh4a/clock-sh7724.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 87 arch/sh/kernel/cpu/sh4a/clock-sh7724.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 154 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 155 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 156 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 158 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 194 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 203 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 204 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 205 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 206 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 207 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 208 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 209 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 210 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 212 arch/sh/kernel/cpu/sh4a/clock-sh7724.c [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 45 arch/sh/kernel/cpu/sh4a/clock-sh7734.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 73 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 74 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 75 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 76 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 77 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 78 arch/sh/kernel/cpu/sh4a/clock-sh7734.c [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 40 arch/sh/kernel/cpu/sh4a/clock-sh7757.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 70 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 71 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 72 arch/sh/kernel/cpu/sh4a/clock-sh7757.c [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 79 arch/sh/kernel/cpu/sh4a/clock-sh7763.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 85 arch/sh/kernel/cpu/sh4a/clock-sh7780.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 43 arch/sh/kernel/cpu/sh4a/clock-sh7785.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 73 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 74 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 75 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 76 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 77 arch/sh/kernel/cpu/sh4a/clock-sh7785.c [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 45 arch/sh/kernel/cpu/sh4a/clock-sh7786.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 73 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 74 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 75 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 76 arch/sh/kernel/cpu/sh4a/clock-sh7786.c [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 39 arch/sh/kernel/cpu/sh4a/clock-shx3.c .flags = CLK_ENABLE_ON_INIT, CLK_ENABLE_ON_INIT 67 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 68 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 69 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 70 arch/sh/kernel/cpu/sh4a/clock-shx3.c [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), CLK_ENABLE_ON_INIT 40 drivers/clk/renesas/clk-r8a7740.c { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT }, CLK_ENABLE_ON_INIT 41 drivers/clk/renesas/clk-r8a7740.c { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT }, CLK_ENABLE_ON_INIT 42 drivers/clk/renesas/clk-r8a7740.c { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT }, CLK_ENABLE_ON_INIT 43 drivers/clk/renesas/clk-r8a7740.c { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT }, CLK_ENABLE_ON_INIT 467 drivers/sh/clk/core.c if (clkp->flags & CLK_ENABLE_ON_INIT) CLK_ENABLE_ON_INIT 362 drivers/sh/clk/cpg.c if (parent->flags & CLK_ENABLE_ON_INIT)