hdlcd_write        44 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
hdlcd_write        53 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
hdlcd_write        63 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
hdlcd_write       103 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
hdlcd_write       115 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
hdlcd_write       120 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
hdlcd_write       122 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
hdlcd_write       150 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
hdlcd_write       153 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
hdlcd_write       154 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
hdlcd_write       155 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
hdlcd_write       156 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
hdlcd_write       157 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
hdlcd_write       158 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
hdlcd_write       159 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
hdlcd_write       160 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
hdlcd_write       161 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
hdlcd_write       177 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
hdlcd_write       187 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
hdlcd_write       273 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
hdlcd_write       274 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
hdlcd_write       275 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
hdlcd_write       276 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
hdlcd_write       151 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
hdlcd_write       160 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
hdlcd_write       161 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
hdlcd_write       173 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
hdlcd_write       192 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);