CLK_DIVIDER_HIWORD_MASK 436 drivers/clk/clk-divider.c if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { CLK_DIVIDER_HIWORD_MASK 477 drivers/clk/clk-divider.c if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { CLK_DIVIDER_HIWORD_MASK 124 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 125 drivers/clk/hisilicon/clk-hi3620.c { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 126 drivers/clk/hisilicon/clk-hi3620.c { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 127 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC1_DIV, "mmc1_div", "mmc1_mux", 0, 0x108, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 128 drivers/clk/hisilicon/clk-hi3620.c { HI3620_HSIC_DIV, "hsic_div", "rclk_hsic", 0, 0x130, 0, 2, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 129 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC2_DIV, "mmc2_div", "mmc2_mux", 0, 0x140, 0, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 130 drivers/clk/hisilicon/clk-hi3620.c { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIVIDER_HIWORD_MASK, NULL, }, CLK_DIVIDER_HIWORD_MASK 336 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 338 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 340 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 342 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 344 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 346 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 348 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 350 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 352 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 354 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 356 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 358 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 360 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 362 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 364 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 366 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 368 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 370 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 372 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 374 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 376 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 378 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 423 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 425 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 427 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 429 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 449 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 451 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 453 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 455 drivers/clk/hisilicon/clk-hi3660.c CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 488 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 490 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 492 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 494 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 496 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 498 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 500 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 502 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 504 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 506 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 508 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 510 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 512 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 514 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 516 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 518 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 520 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 522 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 524 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 526 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 528 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 530 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 532 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 534 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 536 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 538 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 653 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 655 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 657 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 659 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 661 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 663 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 665 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 802 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 804 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 806 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 808 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 810 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 812 drivers/clk/hisilicon/clk-hi3670.c CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, }, CLK_DIVIDER_HIWORD_MASK 125 drivers/clk/rockchip/clk-half-divider.c if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { CLK_DIVIDER_HIWORD_MASK 200 drivers/clk/rockchip/clk-px30.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 144 drivers/clk/rockchip/clk-rk3036.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 169 drivers/clk/rockchip/clk-rk3128.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 236 drivers/clk/rockchip/clk-rk3188.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 179 drivers/clk/rockchip/clk-rk3228.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 240 drivers/clk/rockchip/clk-rk3288.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 195 drivers/clk/rockchip/clk-rk3308.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 232 drivers/clk/rockchip/clk-rk3328.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 152 drivers/clk/rockchip/clk-rk3368.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 239 drivers/clk/rockchip/clk-rk3399.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 162 drivers/clk/rockchip/clk-rv1108.c #define DFLAGS CLK_DIVIDER_HIWORD_MASK CLK_DIVIDER_HIWORD_MASK 257 drivers/clk/ti/divider.c if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { CLK_DIVIDER_HIWORD_MASK 325 drivers/clk/ti/divider.c if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {