gvt_dbg_core       93 drivers/gpu/drm/i915/gvt/aperture_gm.c 	gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
gvt_dbg_core       96 drivers/gpu/drm/i915/gvt/aperture_gm.c 	gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
gvt_dbg_core      186 drivers/gpu/drm/i915/gvt/dmabuf.c 			gvt_dbg_core("invalid drm_format_mod %llx for tiling\n",
gvt_dbg_core      171 drivers/gpu/drm/i915/gvt/fb_decoder.c 				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
gvt_dbg_core      174 drivers/gpu/drm/i915/gvt/fb_decoder.c 			gvt_dbg_core("skl: unsupported tile format:%x\n",
gvt_dbg_core      367 drivers/gpu/drm/i915/gvt/fb_decoder.c 		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
gvt_dbg_core      196 drivers/gpu/drm/i915/gvt/firmware.c 	gvt_dbg_core("Invalid firmware: %s [file] 0x%llx [request] 0x%llx\n",
gvt_dbg_core      245 drivers/gpu/drm/i915/gvt/firmware.c 	gvt_dbg_core("request hw state firmware %s...\n", path);
gvt_dbg_core      253 drivers/gpu/drm/i915/gvt/firmware.c 	gvt_dbg_core("success.\n");
gvt_dbg_core      259 drivers/gpu/drm/i915/gvt/firmware.c 	gvt_dbg_core("verified.\n");
gvt_dbg_core     2125 drivers/gpu/drm/i915/gvt/gtt.c 				gvt_dbg_core("GMA 0x%lx is not present\n", gma);
gvt_dbg_core     2688 drivers/gpu/drm/i915/gvt/gtt.c 	gvt_dbg_core("init gtt\n");
gvt_dbg_core      213 drivers/gpu/drm/i915/gvt/gvt.c 	gvt_dbg_core("service thread start\n");
gvt_dbg_core      316 drivers/gpu/drm/i915/gvt/gvt.c 	gvt_dbg_core("init gvt device\n");
gvt_dbg_core      380 drivers/gpu/drm/i915/gvt/gvt.c 	gvt_dbg_core("gvt device initialization is done\n");
gvt_dbg_core      439 drivers/gpu/drm/i915/gvt/gvt.c 	gvt_dbg_core("Running with hypervisor %s in host mode\n",
gvt_dbg_core      222 drivers/gpu/drm/i915/gvt/handlers.c 			gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
gvt_dbg_core      224 drivers/gpu/drm/i915/gvt/handlers.c 			gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
gvt_dbg_core     1087 drivers/gpu/drm/i915/gvt/handlers.c 	gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
gvt_dbg_core     1457 drivers/gpu/drm/i915/gvt/handlers.c 	gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
gvt_dbg_core     1728 drivers/gpu/drm/i915/gvt/handlers.c 		gvt_dbg_core("EXECLIST %s on ring %d\n",
gvt_dbg_core      427 drivers/gpu/drm/i915/gvt/interrupt.c 		gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
gvt_dbg_core      692 drivers/gpu/drm/i915/gvt/interrupt.c 	gvt_dbg_core("init irq framework\n");
gvt_dbg_core      677 drivers/gpu/drm/i915/gvt/kvmgt.c 	gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
gvt_dbg_core     1281 drivers/gpu/drm/i915/gvt/kvmgt.c 	gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd);
gvt_dbg_core     1370 drivers/gpu/drm/i915/gvt/kvmgt.c 			gvt_dbg_core("get region info bar:%d\n", info.index);
gvt_dbg_core     1379 drivers/gpu/drm/i915/gvt/kvmgt.c 			gvt_dbg_core("get region info index:%d\n", info.index);
gvt_dbg_core      223 drivers/gpu/drm/i915/gvt/mmio_context.c 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
gvt_dbg_core      253 drivers/gpu/drm/i915/gvt/mmio_context.c 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
gvt_dbg_core      280 drivers/gpu/drm/i915/gvt/mmio_context.c 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
gvt_dbg_core      388 drivers/gpu/drm/i915/gvt/mmio_context.c 	gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
gvt_dbg_core      228 drivers/gpu/drm/i915/gvt/opregion.c 	gvt_dbg_core("init vgpu%d opregion\n", vgpu->id);
gvt_dbg_core      300 drivers/gpu/drm/i915/gvt/opregion.c 	gvt_dbg_core("emulate opregion from kernel\n");
gvt_dbg_core      335 drivers/gpu/drm/i915/gvt/opregion.c 	gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id);
gvt_dbg_core      430 drivers/gpu/drm/i915/gvt/sched_policy.c 		gvt_dbg_core("vgpu%d: start schedule\n", vgpu->id);
gvt_dbg_core      454 drivers/gpu/drm/i915/gvt/sched_policy.c 	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);
gvt_dbg_core     1005 drivers/gpu/drm/i915/gvt/scheduler.c 	gvt_dbg_core("workload thread for ring %d started\n", ring_id);
gvt_dbg_core     1090 drivers/gpu/drm/i915/gvt/scheduler.c 	gvt_dbg_core("clean workload scheduler\n");
gvt_dbg_core     1108 drivers/gpu/drm/i915/gvt/scheduler.c 	gvt_dbg_core("init workload scheduler\n");
gvt_dbg_core     1353 drivers/gpu/drm/i915/gvt/scheduler.c 		gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
gvt_dbg_core     1365 drivers/gpu/drm/i915/gvt/scheduler.c 	gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
gvt_dbg_core       65 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
gvt_dbg_core       66 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
gvt_dbg_core       68 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
gvt_dbg_core       70 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
gvt_dbg_core      158 drivers/gpu/drm/i915/gvt/vgpu.c 		gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
gvt_dbg_core      199 drivers/gpu/drm/i915/gvt/vgpu.c 		gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
gvt_dbg_core      371 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
gvt_dbg_core      539 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("------------------------------------------\n");
gvt_dbg_core      540 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
gvt_dbg_core      580 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
gvt_dbg_core      581 drivers/gpu/drm/i915/gvt/vgpu.c 	gvt_dbg_core("------------------------------------------\n");