CLK_BASE           50 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
CLK_BASE           50 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
CLK_BASE           50 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
CLK_BASE           54 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
CLK_BASE           52 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
CLK_BASE           44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c 	CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
CLK_BASE           53 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
CLK_BASE           84 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h 	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
CLK_BASE           47 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE CLK_BASE            ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
CLK_BASE           43 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
CLK_BASE           46 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
CLK_BASE           46 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
CLK_BASE           53 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
CLK_BASE          203 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE CLK_BASE			= { { { { 0x00016C00, 0, 0, 0, 0 } },
CLK_BASE           45 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } },