gmu_write          37 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
gmu_write          61 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
gmu_write         110 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
gmu_write         112 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
gmu_write         119 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
gmu_write         195 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
gmu_write         196 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
gmu_write         212 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
gmu_write         251 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
gmu_write         264 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
gmu_write         274 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
gmu_write         278 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
gmu_write         282 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
gmu_write         294 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
gmu_write         316 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
gmu_write         332 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
gmu_write         337 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
gmu_write         338 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
gmu_write         350 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
gmu_write         357 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
gmu_write         372 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
gmu_write         381 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
gmu_write         400 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
gmu_write         403 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
gmu_write         407 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
gmu_write         416 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
gmu_write         423 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
gmu_write         444 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
gmu_write         447 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
gmu_write         448 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
gmu_write         449 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
gmu_write         450 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
gmu_write         451 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
gmu_write         452 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
gmu_write         453 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
gmu_write         454 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
gmu_write         455 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
gmu_write         456 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
gmu_write         457 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
gmu_write         460 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
gmu_write         461 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
gmu_write         462 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
gmu_write         463 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
gmu_write         464 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
gmu_write         525 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
gmu_write         527 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
gmu_write         531 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
gmu_write         538 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
gmu_write         581 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
gmu_write         596 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 			gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i,
gmu_write         600 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
gmu_write         601 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
gmu_write         604 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova);
gmu_write         605 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
gmu_write         607 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
gmu_write         615 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
gmu_write         658 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
gmu_write         659 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
gmu_write         720 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
gmu_write         721 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
gmu_write         740 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
gmu_write         741 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
gmu_write          98 drivers/gpu/drm/msm/adreno/a6xx_gmu.h 	gmu_write(gmu, reg, val | or);
gmu_write         597 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
gmu_write         673 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
gmu_write          78 drivers/gpu/drm/msm/adreno/a6xx_hfi.c 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);
gmu_write         101 drivers/gpu/drm/msm/adreno/a6xx_hfi.c 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR,