gk20a_clk          65 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
gk20a_clk          77 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
gk20a_clk          89 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
gk20a_clk         101 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate,
gk20a_clk         211 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
gk20a_clk         256 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_enable(struct gk20a_clk *clk)
gk20a_clk         284 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_disable(struct gk20a_clk *clk)
gk20a_clk         296 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
gk20a_clk         335 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
gk20a_clk         462 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         482 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         491 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         507 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk_setup_slide(struct gk20a_clk *clk)
gk20a_clk         546 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         567 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         596 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_clk = {
gk20a_clk         616 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 		struct gk20a_clk *clk)
gk20a_clk         644 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	struct gk20a_clk *clk;
gk20a_clk         652 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 	ret = gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params,
gk20a_clk         125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
gk20a_clk         127 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *);
gk20a_clk         128 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *);
gk20a_clk         129 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *);
gk20a_clk         130 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *);
gk20a_clk         133 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h gk20a_pllg_is_enabled(struct gk20a_clk *clk)
gk20a_clk         143 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)
gk20a_clk         150 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h 		    const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
gk20a_clk         157 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h int gk20a_clk_setup_slide(struct gk20a_clk *);
gk20a_clk         121 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	struct gk20a_clk base;
gk20a_clk         139 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c #define gm20b_clk(p) container_of((gk20a_clk(p)), struct gm20b_clk, base)
gk20a_clk         813 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	struct gk20a_clk *clk = gk20a_clk(base);
gk20a_clk         914 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	struct gk20a_clk *clk;