get_reg_field_value 457 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c field = get_reg_field_value(value, get_reg_field_value 876 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c port_connectivity = get_reg_field_value(value, get_reg_field_value 79 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t field = get_reg_field_value( get_reg_field_value 92 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c uint32_t field = get_reg_field_value( get_reg_field_value 100 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c field = get_reg_field_value(value, get_reg_field_value 145 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c field = get_reg_field_value( get_reg_field_value 357 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c *returned_bytes = get_reg_field_value(value, get_reg_field_value 1377 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN); get_reg_field_value 123 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (get_reg_field_value( get_reg_field_value 276 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { get_reg_field_value 283 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { get_reg_field_value 286 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { get_reg_field_value 150 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c chunk_int = get_reg_field_value( get_reg_field_value 155 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c chunk_mul = get_reg_field_value( get_reg_field_value 478 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c if (get_reg_field_value(value, UNP_GRPH_UPDATE, get_reg_field_value 115 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c bool use_set_a = (get_reg_field_value(cntl_value, get_reg_field_value 556 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c use_set_a = get_reg_field_value( get_reg_field_value 74 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c if (get_reg_field_value(value, get_reg_field_value 77 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c get_reg_field_value(value, get_reg_field_value 101 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); get_reg_field_value 200 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struc_en = get_reg_field_value( get_reg_field_value 205 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c struc_stereo_sel_ovr = get_reg_field_value( get_reg_field_value 513 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t field = get_reg_field_value( get_reg_field_value 537 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c position->horizontal_count = get_reg_field_value( get_reg_field_value 542 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c position->vertical_count = get_reg_field_value( get_reg_field_value 549 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c position->nominal_vcount = get_reg_field_value( get_reg_field_value 578 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c *v_blank_start = get_reg_field_value(value, get_reg_field_value 581 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c *v_blank_end = get_reg_field_value(value, get_reg_field_value 1281 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c check_point = get_reg_field_value(value_crtc_vtotal, get_reg_field_value 1506 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (get_reg_field_value(pol_value, get_reg_field_value 1782 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bool force = get_reg_field_value(value, get_reg_field_value 1785 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bool vert_sync = get_reg_field_value(value1, get_reg_field_value 1973 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c if (get_reg_field_value( get_reg_field_value 1977 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c get_reg_field_value( get_reg_field_value 2094 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c field = get_reg_field_value(value, CRTC_CONTROL, get_reg_field_value 2186 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c field = get_reg_field_value(value, CRTC_CRC_CNTL, CRTC_CRC_EN); get_reg_field_value 2194 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c *r_cr = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_R_CR); get_reg_field_value 2195 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c *g_y = get_reg_field_value(value, CRTC_CRC0_DATA_RG, CRC0_G_Y); get_reg_field_value 2199 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c *b_cb = get_reg_field_value(value, CRTC_CRC0_DATA_B, CRC0_B_CB); get_reg_field_value 149 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK); get_reg_field_value 163 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c h1 = get_reg_field_value( get_reg_field_value 168 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c v1 = get_reg_field_value( get_reg_field_value 175 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c h2 = get_reg_field_value( get_reg_field_value 180 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c v2 = get_reg_field_value( get_reg_field_value 607 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t field = get_reg_field_value( get_reg_field_value 194 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c get_reg_field_value(value, SCLV_MODE, SCL_MODE), get_reg_field_value 199 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN), get_reg_field_value 311 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c if (get_reg_field_value( get_reg_field_value 303 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (get_reg_field_value( get_reg_field_value 450 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { get_reg_field_value 457 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { get_reg_field_value 460 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { get_reg_field_value 476 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c return get_reg_field_value( get_reg_field_value 631 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c channels = get_reg_field_value(value_control, get_reg_field_value 79 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c chunk_int = get_reg_field_value( get_reg_field_value 84 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c chunk_mul = get_reg_field_value( get_reg_field_value 115 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c chunk_int = get_reg_field_value( get_reg_field_value 120 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c chunk_mul = get_reg_field_value( get_reg_field_value 622 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->audio_stream_number = get_reg_field_value(reg_val, get_reg_field_value 625 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->hdmi_disable = get_reg_field_value(reg_val, get_reg_field_value 630 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->dc_pinstraps_audio = get_reg_field_value(reg_val, get_reg_field_value 95 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c field = get_reg_field_value(value, CRTC0_CRTC_STATUS, CRTC_V_BLANK); get_reg_field_value 177 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t field = get_reg_field_value( get_reg_field_value 194 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->horizontal_count = get_reg_field_value(value, get_reg_field_value 197 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->vertical_count = get_reg_field_value(value, get_reg_field_value 205 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->nominal_vcount = get_reg_field_value(value, get_reg_field_value 256 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c get_reg_field_value(value_crtc_vtotal, get_reg_field_value 319 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c if (get_reg_field_value(pol_value, get_reg_field_value 379 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c return get_reg_field_value(value, get_reg_field_value 613 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->horizontal_count = get_reg_field_value( get_reg_field_value 618 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->vertical_count = get_reg_field_value( get_reg_field_value 628 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c position->nominal_vcount = get_reg_field_value( get_reg_field_value 650 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c *v_blank_start = get_reg_field_value(v_blank_start_end, get_reg_field_value 653 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c *v_blank_end = get_reg_field_value(v_blank_start_end, get_reg_field_value 760 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c if (get_reg_field_value( get_reg_field_value 764 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c get_reg_field_value( get_reg_field_value 1125 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c field = get_reg_field_value(value, CRTC0_CRTC_CONTROL, get_reg_field_value 1185 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c field = get_reg_field_value(value, CRTC0_CRTC_CRC_CNTL, CRTC_CRC_EN); get_reg_field_value 1193 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c *r_cr = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_R_CR); get_reg_field_value 1194 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c *g_y = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_RG, CRC0_G_Y); get_reg_field_value 1198 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c *b_cb = get_reg_field_value(value, CRTC0_CRTC_CRC0_DATA_B, CRC0_B_CB); get_reg_field_value 49 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint32_t current_status = get_reg_field_value(value, get_reg_field_value 49 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c get_reg_field_value( get_reg_field_value 49 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c get_reg_field_value( get_reg_field_value 130 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c get_reg_field_value( get_reg_field_value 130 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c get_reg_field_value( get_reg_field_value 131 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c get_reg_field_value(