CLKCTRL           990 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
CLKCTRL           991 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
CLKCTRL           992 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
CLKCTRL           993 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
CLKCTRL           994 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
CLKCTRL           995 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
CLKCTRL           996 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
CLKCTRL           997 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
CLKCTRL           998 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
CLKCTRL           999 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
CLKCTRL          1000 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
CLKCTRL          1001 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
CLKCTRL          1002 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
CLKCTRL          1003 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
CLKCTRL          1004 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
CLKCTRL          1005 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
CLKCTRL          1006 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
CLKCTRL          1007 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
CLKCTRL          1008 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
CLKCTRL          1009 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
CLKCTRL          1010 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL          1011 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_smartreflex0_hwmod,
CLKCTRL          1013 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_smartreflex1_hwmod,
CLKCTRL          1015 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL          1016 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
CLKCTRL          1017 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL          1019 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL          1020 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL          1021 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL          1022 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL          1023 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
CLKCTRL          1024 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
CLKCTRL          1025 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL          1026 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL          1027 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL          1028 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL          1029 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL          1030 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL          1031 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL          1032 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL          1033 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL          1034 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
CLKCTRL          1052 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
CLKCTRL          1053 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
CLKCTRL          1054 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
CLKCTRL          1055 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
CLKCTRL          1056 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
CLKCTRL          1057 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
CLKCTRL          1058 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
CLKCTRL          1059 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
CLKCTRL          1060 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
CLKCTRL          1061 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
CLKCTRL          1062 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
CLKCTRL          1063 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
CLKCTRL          1064 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
CLKCTRL          1065 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
CLKCTRL          1066 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
CLKCTRL          1067 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
CLKCTRL          1068 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
CLKCTRL          1069 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
CLKCTRL          1070 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
CLKCTRL          1071 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
CLKCTRL          1072 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL          1073 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_smartreflex0_hwmod,
CLKCTRL          1075 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_smartreflex1_hwmod,
CLKCTRL          1077 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
CLKCTRL          1078 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
CLKCTRL          1079 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL          1080 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL          1081 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL          1082 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL          1083 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
CLKCTRL          1084 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
CLKCTRL          1085 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
CLKCTRL          1086 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL          1087 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL          1088 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL          1089 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL          1090 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL          1091 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL          1092 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
CLKCTRL          1093 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
CLKCTRL          1094 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
CLKCTRL          1095 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 	CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
CLKCTRL            22 drivers/clk/mxs/clk-imx23.c #define PLLCTRL0		(CLKCTRL + 0x0000)
CLKCTRL            23 drivers/clk/mxs/clk-imx23.c #define CPU			(CLKCTRL + 0x0020)
CLKCTRL            24 drivers/clk/mxs/clk-imx23.c #define HBUS			(CLKCTRL + 0x0030)
CLKCTRL            25 drivers/clk/mxs/clk-imx23.c #define XBUS			(CLKCTRL + 0x0040)
CLKCTRL            26 drivers/clk/mxs/clk-imx23.c #define XTAL			(CLKCTRL + 0x0050)
CLKCTRL            27 drivers/clk/mxs/clk-imx23.c #define PIX			(CLKCTRL + 0x0060)
CLKCTRL            28 drivers/clk/mxs/clk-imx23.c #define SSP			(CLKCTRL + 0x0070)
CLKCTRL            29 drivers/clk/mxs/clk-imx23.c #define GPMI			(CLKCTRL + 0x0080)
CLKCTRL            30 drivers/clk/mxs/clk-imx23.c #define SPDIF			(CLKCTRL + 0x0090)
CLKCTRL            31 drivers/clk/mxs/clk-imx23.c #define EMI			(CLKCTRL + 0x00a0)
CLKCTRL            32 drivers/clk/mxs/clk-imx23.c #define SAIF			(CLKCTRL + 0x00c0)
CLKCTRL            33 drivers/clk/mxs/clk-imx23.c #define TV			(CLKCTRL + 0x00d0)
CLKCTRL            34 drivers/clk/mxs/clk-imx23.c #define ETM			(CLKCTRL + 0x00e0)
CLKCTRL            35 drivers/clk/mxs/clk-imx23.c #define FRAC			(CLKCTRL + 0x00f0)
CLKCTRL            36 drivers/clk/mxs/clk-imx23.c #define CLKSEQ			(CLKCTRL + 0x0110)
CLKCTRL            20 drivers/clk/mxs/clk-imx28.c #define PLL0CTRL0		(CLKCTRL + 0x0000)
CLKCTRL            21 drivers/clk/mxs/clk-imx28.c #define PLL1CTRL0		(CLKCTRL + 0x0020)
CLKCTRL            22 drivers/clk/mxs/clk-imx28.c #define PLL2CTRL0		(CLKCTRL + 0x0040)
CLKCTRL            23 drivers/clk/mxs/clk-imx28.c #define CPU			(CLKCTRL + 0x0050)
CLKCTRL            24 drivers/clk/mxs/clk-imx28.c #define HBUS			(CLKCTRL + 0x0060)
CLKCTRL            25 drivers/clk/mxs/clk-imx28.c #define XBUS			(CLKCTRL + 0x0070)
CLKCTRL            26 drivers/clk/mxs/clk-imx28.c #define XTAL			(CLKCTRL + 0x0080)
CLKCTRL            27 drivers/clk/mxs/clk-imx28.c #define SSP0			(CLKCTRL + 0x0090)
CLKCTRL            28 drivers/clk/mxs/clk-imx28.c #define SSP1			(CLKCTRL + 0x00a0)
CLKCTRL            29 drivers/clk/mxs/clk-imx28.c #define SSP2			(CLKCTRL + 0x00b0)
CLKCTRL            30 drivers/clk/mxs/clk-imx28.c #define SSP3			(CLKCTRL + 0x00c0)
CLKCTRL            31 drivers/clk/mxs/clk-imx28.c #define GPMI			(CLKCTRL + 0x00d0)
CLKCTRL            32 drivers/clk/mxs/clk-imx28.c #define SPDIF			(CLKCTRL + 0x00e0)
CLKCTRL            33 drivers/clk/mxs/clk-imx28.c #define EMI			(CLKCTRL + 0x00f0)
CLKCTRL            34 drivers/clk/mxs/clk-imx28.c #define SAIF0			(CLKCTRL + 0x0100)
CLKCTRL            35 drivers/clk/mxs/clk-imx28.c #define SAIF1			(CLKCTRL + 0x0110)
CLKCTRL            36 drivers/clk/mxs/clk-imx28.c #define LCDIF			(CLKCTRL + 0x0120)
CLKCTRL            37 drivers/clk/mxs/clk-imx28.c #define ETM			(CLKCTRL + 0x0130)
CLKCTRL            38 drivers/clk/mxs/clk-imx28.c #define ENET			(CLKCTRL + 0x0140)
CLKCTRL            39 drivers/clk/mxs/clk-imx28.c #define FLEXCAN			(CLKCTRL + 0x0160)
CLKCTRL            40 drivers/clk/mxs/clk-imx28.c #define FRAC0			(CLKCTRL + 0x01b0)
CLKCTRL            41 drivers/clk/mxs/clk-imx28.c #define FRAC1			(CLKCTRL + 0x01c0)
CLKCTRL            42 drivers/clk/mxs/clk-imx28.c #define CLKSEQ			(CLKCTRL + 0x01d0)
CLKCTRL            44 drivers/staging/media/omap4iss/iss.c 	ISS_PRINT_REGISTER(iss, CLKCTRL);