CLASS2_ENABLE_MAILBOX_INTR   98 arch/powerpc/platforms/cell/spufs/backing_ops.c 				CLASS2_ENABLE_MAILBOX_INTR;
CLASS2_ENABLE_MAILBOX_INTR  132 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
CLASS2_ENABLE_MAILBOX_INTR   65 arch/powerpc/platforms/cell/spufs/hw_ops.c 			spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
CLASS2_ENABLE_MAILBOX_INTR   96 arch/powerpc/platforms/cell/spufs/hw_ops.c 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
CLASS2_ENABLE_MAILBOX_INTR 1684 arch/powerpc/platforms/cell/spufs/switch.c 		spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);