CKSEG1ADDR 112 arch/mips/bcm47xx/prom.c setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); CKSEG1ADDR 34 arch/mips/bmips/setup.c #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) CKSEG1ADDR 13 arch/mips/boot/compressed/uart-16550.c #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) CKSEG1ADDR 18 arch/mips/boot/compressed/uart-16550.c #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) CKSEG1ADDR 23 arch/mips/boot/compressed/uart-16550.c #define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) CKSEG1ADDR 28 arch/mips/boot/compressed/uart-16550.c #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) CKSEG1ADDR 34 arch/mips/boot/compressed/uart-16550.c #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) CKSEG1ADDR 38 arch/mips/cobalt/pci.c .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE), CKSEG1ADDR 20 arch/mips/cobalt/reset.c #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000)) CKSEG1ADDR 83 arch/mips/cobalt/setup.c set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); CKSEG1ADDR 117 arch/mips/cobalt/setup.c setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); CKSEG1ADDR 144 arch/mips/dec/ecc-berr.c (void *)CKSEG1ADDR(address); CKSEG1ADDR 227 arch/mips/dec/ecc-berr.c volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); CKSEG1ADDR 229 arch/mips/dec/ecc-berr.c kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); CKSEG1ADDR 230 arch/mips/dec/ecc-berr.c kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); CKSEG1ADDR 245 arch/mips/dec/ecc-berr.c volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); CKSEG1ADDR 246 arch/mips/dec/ecc-berr.c volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); CKSEG1ADDR 248 arch/mips/dec/ecc-berr.c kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR); CKSEG1ADDR 249 arch/mips/dec/ecc-berr.c kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN); CKSEG1ADDR 49 arch/mips/dec/kn01-berr.c volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); CKSEG1ADDR 62 arch/mips/dec/kn01-berr.c volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + CKSEG1ADDR 150 arch/mips/dec/kn01-berr.c volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); CKSEG1ADDR 177 arch/mips/dec/kn01-berr.c volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); CKSEG1ADDR 30 arch/mips/dec/kn02-irq.c volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + CKSEG1ADDR 39 arch/mips/dec/kn02-irq.c volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + CKSEG1ADDR 62 arch/mips/dec/kn02-irq.c volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + CKSEG1ADDR 29 arch/mips/dec/kn02xa-berr.c volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); CKSEG1ADDR 30 arch/mips/dec/kn02xa-berr.c volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); CKSEG1ADDR 40 arch/mips/dec/kn02xa-berr.c volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); CKSEG1ADDR 41 arch/mips/dec/kn02xa-berr.c volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); CKSEG1ADDR 126 arch/mips/dec/kn02xa-berr.c volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); CKSEG1ADDR 74 arch/mips/dec/prom/identify.c dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); CKSEG1ADDR 82 arch/mips/dec/prom/identify.c dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC); CKSEG1ADDR 91 arch/mips/dec/prom/identify.c dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC); CKSEG1ADDR 100 arch/mips/dec/prom/identify.c ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); CKSEG1ADDR 101 arch/mips/dec/prom/identify.c dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); CKSEG1ADDR 110 arch/mips/dec/prom/identify.c ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL); CKSEG1ADDR 111 arch/mips/dec/prom/identify.c dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY); CKSEG1ADDR 17 arch/mips/dec/reset.c noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000); CKSEG1ADDR 34 arch/mips/fw/sni/sniprom.c #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) CKSEG1ADDR 86 arch/mips/fw/sni/sniprom.c return (void *)CKSEG1ADDR(hwconf); CKSEG1ADDR 19 arch/mips/generic/board-sead3.c #define SEAD_CONFIG CKSEG1ADDR(0x1b100110) CKSEG1ADDR 22 arch/mips/generic/board-sead3.c #define MIPS_REVISION CKSEG1ADDR(0x1fc00010) CKSEG1ADDR 170 arch/mips/include/asm/barrier.h : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \ CKSEG1ADDR 22 arch/mips/include/asm/dec/prom.h #define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000) CKSEG1ADDR 197 arch/mips/include/asm/io.h (unsigned long)CKSEG1ADDR(phys_addr); CKSEG1ADDR 12 arch/mips/include/asm/mach-cobalt/mach-gt64120.h #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE) CKSEG1ADDR 59 arch/mips/include/asm/mach-loongson64/loongson.h (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) CKSEG1ADDR 71 arch/mips/include/asm/netlogic/common.h return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); CKSEG1ADDR 38 arch/mips/include/asm/netlogic/xlr/iomap.h #define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) CKSEG1ADDR 38 arch/mips/include/asm/sni.h #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) CKSEG1ADDR 44 arch/mips/include/asm/sni.h #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) CKSEG1ADDR 45 arch/mips/include/asm/sni.h #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c) CKSEG1ADDR 46 arch/mips/include/asm/sni.h #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014) CKSEG1ADDR 47 arch/mips/include/asm/sni.h #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) CKSEG1ADDR 48 arch/mips/include/asm/sni.h #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024) CKSEG1ADDR 49 arch/mips/include/asm/sni.h #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c) CKSEG1ADDR 50 arch/mips/include/asm/sni.h #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) CKSEG1ADDR 51 arch/mips/include/asm/sni.h #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c) CKSEG1ADDR 52 arch/mips/include/asm/sni.h #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) CKSEG1ADDR 53 arch/mips/include/asm/sni.h #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c) CKSEG1ADDR 54 arch/mips/include/asm/sni.h #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) CKSEG1ADDR 63 arch/mips/include/asm/sni.h #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) CKSEG1ADDR 64 arch/mips/include/asm/sni.h #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064) CKSEG1ADDR 65 arch/mips/include/asm/sni.h #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) CKSEG1ADDR 66 arch/mips/include/asm/sni.h #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074) CKSEG1ADDR 67 arch/mips/include/asm/sni.h #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */ CKSEG1ADDR 68 arch/mips/include/asm/sni.h #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */ CKSEG1ADDR 69 arch/mips/include/asm/sni.h #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084) CKSEG1ADDR 70 arch/mips/include/asm/sni.h #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c) CKSEG1ADDR 71 arch/mips/include/asm/sni.h #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094) CKSEG1ADDR 72 arch/mips/include/asm/sni.h #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c) CKSEG1ADDR 73 arch/mips/include/asm/sni.h #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4) CKSEG1ADDR 78 arch/mips/include/asm/sni.h #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000) CKSEG1ADDR 79 arch/mips/include/asm/sni.h #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008) CKSEG1ADDR 80 arch/mips/include/asm/sni.h #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010) CKSEG1ADDR 81 arch/mips/include/asm/sni.h #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018) CKSEG1ADDR 82 arch/mips/include/asm/sni.h #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020) CKSEG1ADDR 83 arch/mips/include/asm/sni.h #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028) CKSEG1ADDR 84 arch/mips/include/asm/sni.h #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030) CKSEG1ADDR 85 arch/mips/include/asm/sni.h #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038) CKSEG1ADDR 86 arch/mips/include/asm/sni.h #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040) CKSEG1ADDR 87 arch/mips/include/asm/sni.h #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048) CKSEG1ADDR 88 arch/mips/include/asm/sni.h #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050) CKSEG1ADDR 97 arch/mips/include/asm/sni.h #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058) CKSEG1ADDR 98 arch/mips/include/asm/sni.h #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060) CKSEG1ADDR 99 arch/mips/include/asm/sni.h #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068) CKSEG1ADDR 100 arch/mips/include/asm/sni.h #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070) CKSEG1ADDR 101 arch/mips/include/asm/sni.h #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */ CKSEG1ADDR 102 arch/mips/include/asm/sni.h #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */ CKSEG1ADDR 103 arch/mips/include/asm/sni.h #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080) CKSEG1ADDR 104 arch/mips/include/asm/sni.h #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088) CKSEG1ADDR 105 arch/mips/include/asm/sni.h #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090) CKSEG1ADDR 106 arch/mips/include/asm/sni.h #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098) CKSEG1ADDR 107 arch/mips/include/asm/sni.h #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0) CKSEG1ADDR 110 arch/mips/include/asm/sni.h #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100) CKSEG1ADDR 120 arch/mips/include/asm/sni.h #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000) CKSEG1ADDR 121 arch/mips/include/asm/sni.h #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000) CKSEG1ADDR 122 arch/mips/include/asm/sni.h #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000) CKSEG1ADDR 123 arch/mips/include/asm/sni.h #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000) CKSEG1ADDR 124 arch/mips/include/asm/sni.h #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000) CKSEG1ADDR 125 arch/mips/include/asm/sni.h #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000) CKSEG1ADDR 126 arch/mips/include/asm/sni.h #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000) CKSEG1ADDR 127 arch/mips/include/asm/sni.h #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000) CKSEG1ADDR 128 arch/mips/include/asm/sni.h #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000) CKSEG1ADDR 129 arch/mips/include/asm/sni.h #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000) CKSEG1ADDR 130 arch/mips/include/asm/sni.h #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000) CKSEG1ADDR 131 arch/mips/include/asm/sni.h #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000) CKSEG1ADDR 132 arch/mips/include/asm/sni.h #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000) CKSEG1ADDR 133 arch/mips/include/asm/sni.h #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000) CKSEG1ADDR 134 arch/mips/include/asm/sni.h #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000) CKSEG1ADDR 135 arch/mips/include/asm/sni.h #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000) CKSEG1ADDR 140 arch/mips/include/asm/sni.h #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) CKSEG1ADDR 141 arch/mips/include/asm/sni.h #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) CKSEG1ADDR 142 arch/mips/include/asm/sni.h #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) CKSEG1ADDR 147 arch/mips/include/asm/sni.h #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) CKSEG1ADDR 189 arch/mips/include/asm/sni.h #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000) CKSEG1ADDR 192 arch/mips/include/asm/sni.h #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000) CKSEG1ADDR 207 arch/mips/include/asm/sni.h #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) CKSEG1ADDR 19 arch/mips/include/asm/vga.h #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x)) CKSEG1ADDR 77 arch/mips/jazz/jazzdma.c pgtbl = (VDMA_PGTBL_ENTRY *)CKSEG1ADDR((unsigned long)pgtbl); CKSEG1ADDR 107 arch/mips/kernel/smp-cps.c core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); CKSEG1ADDR 223 arch/mips/kernel/smp-cps.c write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); CKSEG1ADDR 324 arch/mips/kernel/smp-cps.c core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); CKSEG1ADDR 2251 arch/mips/kernel/traps.c unsigned long uncached_ebase = CKSEG1ADDR(ebase); CKSEG1ADDR 3101 arch/mips/kvm/vz.c vcpu->arch.pc = CKSEG1ADDR(0x1fc00000); CKSEG1ADDR 46 arch/mips/lib/uncached.c usp = CKSEG1ADDR(sp); CKSEG1ADDR 58 arch/mips/lib/uncached.c ufunc = CKSEG1ADDR(lfunc); CKSEG1ADDR 673 arch/mips/loongson64/loongson-3/smp.c (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead); CKSEG1ADDR 680 arch/mips/loongson64/loongson-3/smp.c (void *)CKSEG1ADDR((unsigned long)loongson3a_r2r3_play_dead); CKSEG1ADDR 685 arch/mips/loongson64/loongson-3/smp.c (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead); CKSEG1ADDR 152 arch/mips/mm/ioremap.c return (void __iomem *) CKSEG1ADDR(phys_addr); CKSEG1ADDR 194 arch/mips/mti-malta/malta-dtshim.c config = readl((void __iomem *)CKSEG1ADDR(ROCIT_CONFIG_GEN1)); CKSEG1ADDR 121 arch/mips/mti-malta/malta-setup.c cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); CKSEG1ADDR 164 arch/mips/netlogic/xlp/setup.c nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); CKSEG1ADDR 171 arch/mips/netlogic/xlp/setup.c reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); CKSEG1ADDR 193 arch/mips/netlogic/xlr/setup.c reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); CKSEG1ADDR 19 arch/mips/pci/ops-bonito64.c #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) CKSEG1ADDR 27 arch/mips/pci/ops-loongson2.c (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) CKSEG1ADDR 121 arch/mips/pci/pci-ip32.c .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO), CKSEG1ADDR 277 arch/mips/sgi-ip22/ip22-gio.c ptr32 = (void *)CKSEG1ADDR(addr); CKSEG1ADDR 287 arch/mips/sgi-ip22/ip22-gio.c ptr8 = (void *)CKSEG1ADDR(addr + 3); CKSEG1ADDR 298 arch/mips/sgi-ip22/ip22-gio.c ptr16 = (void *)CKSEG1ADDR(addr + 2); CKSEG1ADDR 319 arch/mips/sgi-ip22/ip22-gio.c ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); CKSEG1ADDR 424 arch/mips/sni/rm200.c #define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000) CKSEG1ADDR 425 arch/mips/sni/rm200.c #define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000) CKSEG1ADDR 419 drivers/bus/mips_cdmm.c bus->regs = (void __iomem *)CKSEG1ADDR(bus->phys); CKSEG1ADDR 88 drivers/mtd/devices/ms02-nv.c ms02nv_diagp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_DIAG)); CKSEG1ADDR 89 drivers/mtd/devices/ms02-nv.c ms02nv_magicp = (ms02nv_uint *)(CKSEG1ADDR(addr + MS02NV_MAGIC)); CKSEG1ADDR 277 drivers/mtd/devices/ms02-nv.c csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); CKSEG1ADDR 283 drivers/mtd/devices/ms02-nv.c csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); CKSEG1ADDR 1069 drivers/net/ethernet/amd/declance.c dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE); CKSEG1ADDR 1075 drivers/net/ethernet/amd/declance.c dev->mem_start = CKSEG1ADDR(0x00020000); CKSEG1ADDR 1078 drivers/net/ethernet/amd/declance.c esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR); CKSEG1ADDR 1125 drivers/net/ethernet/amd/declance.c dev->mem_start = CKSEG1ADDR(start); CKSEG1ADDR 1154 drivers/net/ethernet/amd/declance.c dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE); CKSEG1ADDR 1155 drivers/net/ethernet/amd/declance.c dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM); CKSEG1ADDR 1157 drivers/net/ethernet/amd/declance.c esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);