ffreg_t 643 drivers/atm/iphase.h ffreg_t idlehead_high; /* Idle cell header (high) */ ffreg_t 644 drivers/atm/iphase.h ffreg_t idlehead_low; /* Idle cell header (low) */ ffreg_t 645 drivers/atm/iphase.h ffreg_t maxrate; /* Maximum rate */ ffreg_t 646 drivers/atm/iphase.h ffreg_t stparms; /* Traffic Management Parameters */ ffreg_t 647 drivers/atm/iphase.h ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */ ffreg_t 648 drivers/atm/iphase.h ffreg_t rm_type; /* */ ffreg_t 650 drivers/atm/iphase.h ffreg_t cmd_reg; /* Command register */ ffreg_t 652 drivers/atm/iphase.h ffreg_t cbr_base; /* CBR Pointer Base */ ffreg_t 653 drivers/atm/iphase.h ffreg_t vbr_base; /* VBR Pointer Base */ ffreg_t 654 drivers/atm/iphase.h ffreg_t abr_base; /* ABR Pointer Base */ ffreg_t 655 drivers/atm/iphase.h ffreg_t ubr_base; /* UBR Pointer Base */ ffreg_t 657 drivers/atm/iphase.h ffreg_t vbrwq_base; /* VBR Wait Queue Base */ ffreg_t 658 drivers/atm/iphase.h ffreg_t abrwq_base; /* ABR Wait Queue Base */ ffreg_t 659 drivers/atm/iphase.h ffreg_t ubrwq_base; /* UBR Wait Queue Base */ ffreg_t 660 drivers/atm/iphase.h ffreg_t vct_base; /* Main VC Table Base */ ffreg_t 661 drivers/atm/iphase.h ffreg_t vcte_base; /* Extended Main VC Table Base */ ffreg_t 663 drivers/atm/iphase.h ffreg_t cbr_tab_beg; /* CBR Table Begin */ ffreg_t 664 drivers/atm/iphase.h ffreg_t cbr_tab_end; /* CBR Table End */ ffreg_t 665 drivers/atm/iphase.h ffreg_t cbr_pointer; /* CBR Pointer */ ffreg_t 667 drivers/atm/iphase.h ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */ ffreg_t 668 drivers/atm/iphase.h ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */ ffreg_t 669 drivers/atm/iphase.h ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ ffreg_t 670 drivers/atm/iphase.h ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */ ffreg_t 671 drivers/atm/iphase.h ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/ ffreg_t 672 drivers/atm/iphase.h ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */ ffreg_t 673 drivers/atm/iphase.h ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ ffreg_t 674 drivers/atm/iphase.h ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/ ffreg_t 676 drivers/atm/iphase.h ffreg_t queue_base; /* Base address for PRQ and TCQ */ ffreg_t 677 drivers/atm/iphase.h ffreg_t desc_base; /* Base address of descriptor table */ ffreg_t 679 drivers/atm/iphase.h ffreg_t mode_reg_0; /* Mode register 0 */ ffreg_t 680 drivers/atm/iphase.h ffreg_t mode_reg_1; /* Mode register 1 */ ffreg_t 681 drivers/atm/iphase.h ffreg_t intr_status_reg;/* Interrupt Status register */ ffreg_t 682 drivers/atm/iphase.h ffreg_t mask_reg; /* Mask Register */ ffreg_t 683 drivers/atm/iphase.h ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */ ffreg_t 684 drivers/atm/iphase.h ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */ ffreg_t 685 drivers/atm/iphase.h ffreg_t state_reg; /* Status register */ ffreg_t 687 drivers/atm/iphase.h ffreg_t curr_desc_num; /* Contains the current descriptor num */ ffreg_t 688 drivers/atm/iphase.h ffreg_t next_desc; /* Next descriptor */ ffreg_t 689 drivers/atm/iphase.h ffreg_t next_vc; /* Next VC */ ffreg_t 691 drivers/atm/iphase.h ffreg_t present_slot_cnt;/* Present slot count */ ffreg_t 693 drivers/atm/iphase.h ffreg_t new_desc_num; /* New descriptor number */ ffreg_t 694 drivers/atm/iphase.h ffreg_t new_vc; /* New VC */ ffreg_t 695 drivers/atm/iphase.h ffreg_t sched_tbl_ptr; /* Schedule table pointer */ ffreg_t 696 drivers/atm/iphase.h ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */ ffreg_t 697 drivers/atm/iphase.h ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */ ffreg_t 698 drivers/atm/iphase.h ffreg_t abrwq_wptr; /* ABR wait queue write pointer */ ffreg_t 699 drivers/atm/iphase.h ffreg_t abrwq_rptr; /* ABR wait queue read pointer */ ffreg_t 700 drivers/atm/iphase.h ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */ ffreg_t 701 drivers/atm/iphase.h ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */ ffreg_t 702 drivers/atm/iphase.h ffreg_t cbr_vc; /* CBR VC */ ffreg_t 703 drivers/atm/iphase.h ffreg_t vbr_sb_vc; /* VBR SB VC */ ffreg_t 704 drivers/atm/iphase.h ffreg_t abr_sb_vc; /* ABR SB VC */ ffreg_t 705 drivers/atm/iphase.h ffreg_t ubr_sb_vc; /* UBR SB VC */ ffreg_t 706 drivers/atm/iphase.h ffreg_t vbr_next_link; /* VBR next link */ ffreg_t 707 drivers/atm/iphase.h ffreg_t abr_next_link; /* ABR next link */ ffreg_t 708 drivers/atm/iphase.h ffreg_t ubr_next_link; /* UBR next link */ ffreg_t 710 drivers/atm/iphase.h ffreg_t out_rate_head; /* Out of rate head */ ffreg_t 712 drivers/atm/iphase.h ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */ ffreg_t 713 drivers/atm/iphase.h ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */