fetch_reg 144 arch/sparc/kernel/unaligned_32.c return (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); fetch_reg 147 arch/sparc/kernel/unaligned_32.c return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); fetch_reg 190 arch/sparc/kernel/unaligned_32.c zero[1] = fetch_reg(1, regs); fetch_reg 179 arch/sparc/kernel/unaligned_64.c addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn)); fetch_reg 182 arch/sparc/kernel/unaligned_64.c addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); fetch_reg 213 arch/sparc/kernel/unaligned_64.c (unsigned int)fetch_reg(reg_num, regs) : 0)) << 32) | fetch_reg 214 arch/sparc/kernel/unaligned_64.c (unsigned int)fetch_reg(reg_num + 1, regs); fetch_reg 408 arch/sparc/kernel/unaligned_64.c value = fetch_reg(insn & 0x1f, regs); fetch_reg 300 arch/sparc/kernel/visemul.c orig_rs1 = rs1 = fetch_reg(RS1(insn), regs); fetch_reg 301 arch/sparc/kernel/visemul.c orig_rs2 = rs2 = fetch_reg(RS2(insn), regs); fetch_reg 378 arch/sparc/kernel/visemul.c rs1 = fetch_reg(RS1(insn), regs); fetch_reg 379 arch/sparc/kernel/visemul.c rs2 = fetch_reg(RS2(insn), regs); fetch_reg 411 arch/sparc/kernel/visemul.c rs1 = fetch_reg(RS1(insn), regs); fetch_reg 412 arch/sparc/kernel/visemul.c rs2 = fetch_reg(RS2(insn), regs);