falcon 87 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h int (*enable)(struct nvkm_falcon *falcon); falcon 88 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h void (*disable)(struct nvkm_falcon *falcon); falcon 94 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr) falcon 96 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h return nvkm_rd32(falcon->owner->device, falcon->addr + addr); falcon 100 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data) falcon 102 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_wr32(falcon->owner->device, falcon->addr + addr, data); falcon 106 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val) falcon 108 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h struct nvkm_device *device = falcon->owner->device; falcon 110 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h return nvkm_mask(device, falcon->addr + addr, mask, val); falcon 11 drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h struct nvkm_falcon *falcon; falcon 10 drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h struct nvkm_falcon *falcon; falcon 10 drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h struct nvkm_falcon *falcon; falcon 10 drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h struct nvkm_falcon *falcon; falcon 32 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); falcon 35 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c while (falcon->func->sclass[c].oclass) { falcon 37 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c oclass->base = falcon->func->sclass[index]; falcon 61 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(engine); falcon 62 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_subdev *subdev = &falcon->engine.subdev; falcon 64 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; falcon 74 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->func->intr) { falcon 75 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->func->intr(falcon, chan); falcon 98 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(engine); falcon 99 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_device *device = falcon->engine.subdev.device; falcon 100 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; falcon 103 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_memory_unref(&falcon->core); falcon 104 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->external) { falcon 105 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c vfree(falcon->data.data); falcon 106 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c vfree(falcon->code.data); falcon 107 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.data = NULL; falcon 131 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(engine); falcon 132 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_subdev *subdev = &falcon->engine.subdev; falcon 134 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; falcon 140 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->version = 0; falcon 141 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; falcon 144 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->version = (caps & 0x0000000f); falcon 145 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->secret = (caps & 0x00000030) >> 4; falcon 149 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.limit = (caps & 0x000001ff) << 8; falcon 150 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.limit = (caps & 0x0003fe00) >> 1; falcon 152 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_debug(subdev, "falcon version: %d\n", falcon->version); falcon 153 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_debug(subdev, "secret level: %d\n", falcon->secret); falcon 154 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_debug(subdev, "code limit: %d\n", falcon->code.limit); falcon 155 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_debug(subdev, "data limit: %d\n", falcon->data.limit); falcon 162 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon = nvkm_falcon(engine); falcon 163 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_subdev *subdev = &falcon->engine.subdev; falcon 167 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c const u32 base = falcon->addr; falcon 171 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->secret && falcon->version < 4) { falcon 172 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->version) { falcon 192 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->code.data) { falcon 194 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c device->chipset, falcon->addr >> 12); falcon 198 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.data = vmemdup(fw->data, fw->size); falcon 199 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.size = fw->size; falcon 200 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.data = NULL; falcon 201 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.size = 0; falcon 205 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->external = true; falcon 211 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->code.data) { falcon 213 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c device->chipset, falcon->addr >> 12); falcon 221 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.data = vmemdup(fw->data, fw->size); falcon 222 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.size = fw->size; falcon 224 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->data.data) falcon 228 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c device->chipset, falcon->addr >> 12); falcon 236 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.data = vmemdup(fw->data, fw->size); falcon 237 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.size = fw->size; falcon 239 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->code.data) falcon 243 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_debug(subdev, "firmware: %s (%s)\n", name, falcon->data.data ? falcon 247 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!falcon->data.data && !falcon->core) { falcon 249 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.size, 256, false, falcon 250 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c &falcon->core); falcon 256 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_kmap(falcon->core); falcon 257 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (i = 0; i < falcon->code.size; i += 4) falcon 258 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wo32(falcon->core, i, falcon->code.data[i / 4]); falcon 259 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_done(falcon->core); falcon 263 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->core) { falcon 264 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c u64 addr = nvkm_memory_addr(falcon->core); falcon 274 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->code.size > falcon->code.limit || falcon 275 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.size > falcon->data.limit) { falcon 280 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->version < 3) { falcon 282 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (i = 0; i < falcon->code.size / 4; i++) falcon 283 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff4, falcon->code.data[i]); falcon 286 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (i = 0; i < falcon->code.size / 4; i++) { falcon 289 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x184, falcon->code.data[i]); falcon 295 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->version < 3) { falcon 297 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) falcon 298 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0xff4, falcon->data.data[i]); falcon 299 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (; i < falcon->data.limit; i += 4) falcon 303 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) falcon 304 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c nvkm_wr32(device, base + 0x1c4, falcon->data.data[i]); falcon 305 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c for (; i < falcon->data.limit / 4; i++) falcon 315 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (falcon->func->init) falcon 316 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->func->init(falcon); falcon 342 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c struct nvkm_falcon *falcon; falcon 344 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c if (!(falcon = kzalloc(sizeof(*falcon), GFP_KERNEL))) falcon 346 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->func = func; falcon 347 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->addr = addr; falcon 348 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.data = func->code.data; falcon 349 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->code.size = func->code.size; falcon 350 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.data = func->data.data; falcon 351 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c falcon->data.size = func->data.size; falcon 352 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c *pengine = &falcon->engine; falcon 355 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c enable, &falcon->engine); falcon 1638 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fw(struct nvkm_falcon *falcon, falcon 1641 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); falcon 1642 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); falcon 1648 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 falcon, u32 starstar, u32 base) falcon 1656 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); falcon 1657 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c star = nvkm_rd32(device, falcon + 0x01c4); falcon 1658 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c temp = nvkm_rd32(device, falcon + 0x01c4); falcon 1661 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); falcon 1670 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c4, data); falcon 1682 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); falcon 1683 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); falcon 1684 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, falcon + 0x01c4, star + 4); falcon 1704 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fw(gr->fecs.falcon, &gr->fuc409c, &gr->fuc409d); falcon 1709 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fw(gr->gpccs.falcon, &gr->fuc41ac, &gr->fuc41ad); falcon 1724 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_start(gr->gpccs.falcon); falcon 1725 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_start(gr->fecs.falcon); falcon 1787 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_dmem(gr->fecs.falcon, falcon 1790 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_imem(gr->fecs.falcon, falcon 1795 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_dmem(gr->gpccs.falcon, falcon 1798 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_imem(gr->gpccs.falcon, falcon 1946 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs.falcon); falcon 1952 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs.falcon); falcon 2021 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_get(gr->fecs.falcon, subdev); falcon 2025 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_get(gr->gpccs.falcon, subdev); falcon 2037 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_put(gr->gpccs.falcon, subdev); falcon 2038 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_put(gr->fecs.falcon, subdev); falcon 2064 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_del(&gr->gpccs.falcon); falcon 2065 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_del(&gr->fecs.falcon); falcon 86 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h struct nvkm_falcon *falcon; falcon 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h struct nvkm_falcon *falcon; falcon 39 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c &nvdec->falcon); falcon 46 drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c nvkm_falcon_del(&nvdec->falcon); falcon 33 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c nvkm_falcon_del(&sec2->falcon); falcon 86 drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c return nvkm_falcon_v1_new(subdev, "SEC2", sec2->addr, &sec2->falcon); falcon 27 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, falcon 30 drivers/gpu/drm/nouveau/nvkm/falcon/base.c if (secure && !falcon->secret) { falcon 31 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_warn(falcon->user, falcon 36 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->load_imem(falcon, data, start, size, tag, port, falcon 41 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, falcon 44 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_lock(&falcon->dmem_mutex); falcon 46 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->load_dmem(falcon, data, start, size, port); falcon 48 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_unlock(&falcon->dmem_mutex); falcon 52 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, u8 port, falcon 55 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_lock(&falcon->dmem_mutex); falcon 57 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->read_dmem(falcon, start, size, port, data); falcon 59 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_unlock(&falcon->dmem_mutex); falcon 63 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *inst) falcon 65 drivers/gpu/drm/nouveau/nvkm/falcon/base.c if (!falcon->func->bind_context) { falcon 66 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_error(falcon->user, falcon 71 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->bind_context(falcon, inst); falcon 75 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr) falcon 77 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->set_start_addr(falcon, start_addr); falcon 81 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_start(struct nvkm_falcon *falcon) falcon 83 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->start(falcon); falcon 87 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_enable(struct nvkm_falcon *falcon) falcon 89 drivers/gpu/drm/nouveau/nvkm/falcon/base.c struct nvkm_device *device = falcon->owner->device; falcon 90 drivers/gpu/drm/nouveau/nvkm/falcon/base.c enum nvkm_devidx id = falcon->owner->index; falcon 94 drivers/gpu/drm/nouveau/nvkm/falcon/base.c ret = falcon->func->enable(falcon); falcon 104 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_disable(struct nvkm_falcon *falcon) falcon 106 drivers/gpu/drm/nouveau/nvkm/falcon/base.c struct nvkm_device *device = falcon->owner->device; falcon 107 drivers/gpu/drm/nouveau/nvkm/falcon/base.c enum nvkm_devidx id = falcon->owner->index; falcon 113 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func->disable(falcon); falcon 119 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_reset(struct nvkm_falcon *falcon) falcon 121 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_disable(falcon); falcon 122 drivers/gpu/drm/nouveau/nvkm/falcon/base.c return nvkm_falcon_enable(falcon); falcon 126 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) falcon 128 drivers/gpu/drm/nouveau/nvkm/falcon/base.c return falcon->func->wait_for_halt(falcon, ms); falcon 132 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) falcon 134 drivers/gpu/drm/nouveau/nvkm/falcon/base.c return falcon->func->clear_interrupt(falcon, mask); falcon 138 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_put(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) falcon 140 drivers/gpu/drm/nouveau/nvkm/falcon/base.c if (unlikely(!falcon)) falcon 143 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_lock(&falcon->mutex); falcon 144 drivers/gpu/drm/nouveau/nvkm/falcon/base.c if (falcon->user == user) { falcon 145 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_debug(falcon->user, "released %s falcon\n", falcon->name); falcon 146 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->user = NULL; falcon 148 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_unlock(&falcon->mutex); falcon 152 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_get(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) falcon 154 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_lock(&falcon->mutex); falcon 155 drivers/gpu/drm/nouveau/nvkm/falcon/base.c if (falcon->user) { falcon 157 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->name, nvkm_subdev_name[falcon->user->index]); falcon 158 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_unlock(&falcon->mutex); falcon 162 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_debug(user, "acquired %s falcon\n", falcon->name); falcon 163 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->user = user; falcon 164 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_unlock(&falcon->mutex); falcon 171 drivers/gpu/drm/nouveau/nvkm/falcon/base.c struct nvkm_falcon *falcon) falcon 176 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->func = func; falcon 177 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->owner = subdev; falcon 178 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->name = name; falcon 179 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->addr = addr; falcon 180 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_init(&falcon->mutex); falcon 181 drivers/gpu/drm/nouveau/nvkm/falcon/base.c mutex_init(&falcon->dmem_mutex); falcon 183 drivers/gpu/drm/nouveau/nvkm/falcon/base.c reg = nvkm_falcon_rd32(falcon, 0x12c); falcon 184 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->version = reg & 0xf; falcon 185 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->secret = (reg >> 4) & 0x3; falcon 186 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->code.ports = (reg >> 8) & 0xf; falcon 187 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->data.ports = (reg >> 12) & 0xf; falcon 189 drivers/gpu/drm/nouveau/nvkm/falcon/base.c reg = nvkm_falcon_rd32(falcon, 0x108); falcon 190 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->code.limit = (reg & 0x1ff) << 8; falcon 191 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->data.limit = (reg & 0x3fe00) >> 1; falcon 205 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->has_emem = true; falcon 218 drivers/gpu/drm/nouveau/nvkm/falcon/base.c u32 val = nvkm_falcon_rd32(falcon, debug_reg); falcon 219 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->debug = (val >> 20) & 0x1; falcon 38 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 42 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c queue->position = nvkm_falcon_rd32(falcon, queue->tail_reg); falcon 51 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 54 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_wr32(falcon, queue->tail_reg, queue->position); falcon 62 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 65 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c head = nvkm_falcon_rd32(falcon, queue->head_reg); falcon 66 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c tail = nvkm_falcon_rd32(falcon, queue->tail_reg); falcon 75 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 76 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 79 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c head = nvkm_falcon_rd32(falcon, queue->head_reg); falcon 98 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_read_dmem(priv->falcon, tail, size, 0, data); falcon 108 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 158 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 163 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c head = nvkm_falcon_rd32(falcon, queue->head_reg); falcon 164 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c tail = nvkm_falcon_rd32(falcon, queue->tail_reg); falcon 186 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_load_dmem(priv->falcon, data, queue->position, size, 0); falcon 198 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 217 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 218 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 229 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c queue->position = nvkm_falcon_rd32(falcon, queue->head_reg); falcon 241 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 244 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_wr32(falcon, queue->head_reg, queue->position); falcon 253 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 280 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 359 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 385 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon = priv->falcon; falcon 386 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = falcon->owner; falcon 395 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c switch (falcon->owner->index) { falcon 404 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_subdev_name[falcon->owner->index]); falcon 412 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c tail = nvkm_falcon_rd32(falcon, tail_reg); falcon 413 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_read_dmem(falcon, tail, HDR_SIZE, 0, hdr); falcon 420 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_read_dmem(falcon, tail + HDR_SIZE, hdr->size - HDR_SIZE, 0, falcon 424 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_falcon_wr32(falcon, tail_reg, tail); falcon 469 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c unsigned long falcon; falcon 483 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) { falcon 484 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c int ret = queue->func->acr_func->boot_falcon(queue, falcon); falcon 494 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c nvkm_msgqueue_new(u32 version, struct nvkm_falcon *falcon, falcon 497 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = falcon->owner; falcon 502 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c ret = msgqueue_0137c63d_new(falcon, sb, queue); falcon 505 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c ret = msgqueue_0137bca5_new(falcon, sb, queue); falcon 510 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c ret = msgqueue_0148cdec_new(falcon, sb, queue); falcon 539 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c const struct nvkm_subdev *subdev = queue->falcon->owner; falcon 563 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c struct nvkm_falcon *falcon, falcon 569 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c queue->falcon = falcon; falcon 187 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.h struct nvkm_falcon *falcon; falcon 60 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = priv->base.falcon->owner; falcon 139 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = _queue->falcon->owner; falcon 203 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = queue->falcon->owner; falcon 252 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 269 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon) falcon 289 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c cmd.falcon_id = falcon; falcon 308 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 390 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c msgqueue_0137c63d_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, falcon 401 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c nvkm_msgqueue_ctor(&msgqueue_0137c63d_func, falcon, &ret->base); falcon 416 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c msgqueue_0137bca5_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, falcon 433 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c nvkm_msgqueue_ctor(&msgqueue_0137bca5_func, falcon, &ret->base.base); falcon 108 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c const struct nvkm_subdev *subdev = _queue->falcon->owner; falcon 174 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c const struct nvkm_subdev *subdev = priv->falcon->owner; falcon 199 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon) falcon 219 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c cmd.falcon_id = falcon; falcon 250 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c msgqueue_0148cdec_new(struct nvkm_falcon *falcon, const struct nvkm_secboot *sb, falcon 261 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c nvkm_msgqueue_ctor(&msgqueue_0148cdec_func, falcon, &ret->base); falcon 29 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, falcon 39 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); falcon 43 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); falcon 44 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); falcon 56 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); falcon 57 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x184 + (port * 16), falcon 64 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0); falcon 68 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_load_emem(struct nvkm_falcon *falcon, void *data, u32 start, falcon 76 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 24)); falcon 78 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), ((u32 *)data)[i]); falcon 87 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0xac4 + (port * 8), falcon 95 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, falcon 101 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c if (start >= EMEM_START_ADDR && falcon->has_emem) falcon 102 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c return nvkm_falcon_v1_load_emem(falcon, data, falcon 108 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24)); falcon 110 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]); falcon 119 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), falcon 125 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_read_emem(struct nvkm_falcon *falcon, u32 start, u32 size, falcon 133 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0xac0 + (port * 8), start | (0x1 << 25)); falcon 135 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8)); falcon 142 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 extra = nvkm_falcon_rd32(falcon, 0xac4 + (port * 8)); falcon 152 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, falcon 158 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c if (start >= EMEM_START_ADDR && falcon->has_emem) falcon 159 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c return nvkm_falcon_v1_read_emem(falcon, start - EMEM_START_ADDR, falcon 164 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 25)); falcon 166 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8)); falcon 173 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 extra = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8)); falcon 183 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_memory *ctx) falcon 185 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_device *device = falcon->owner->device; falcon 191 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x10c, 0x0); falcon 195 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c switch (falcon->owner->index) { falcon 209 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x10c, 0x1); falcon 212 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_UCODE, 0x4); falcon 213 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_VIRT, 0x0); falcon 215 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_VID, 0x4); falcon 216 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5); falcon 217 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, fbif + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6); falcon 230 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1); falcon 231 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x054, falcon 235 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x090, 0x10000, 0x10000); falcon 236 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x0a4, 0x8, 0x8); falcon 249 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c switch (falcon->owner->index) { falcon 253 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 irqstat = nvkm_falcon_rd32(falcon, 0x008); falcon 254 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); falcon 260 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x004, 0x00000008, 0x00000008); falcon 261 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x058, 0x00000002, 0x00000002); falcon 264 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 flcn0dc = nvkm_falcon_rd32(falcon, 0x0dc); falcon 275 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr) falcon 277 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x104, start_addr); falcon 281 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_start(struct nvkm_falcon *falcon) falcon 283 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 reg = nvkm_falcon_rd32(falcon, 0x100); falcon 286 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x130, 0x2); falcon 288 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x100, 0x2); falcon 292 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) falcon 294 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_device *device = falcon->owner->device; falcon 297 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10); falcon 305 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) falcon 307 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_device *device = falcon->owner->device; falcon 311 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x004, mask, mask); falcon 313 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0); falcon 321 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c falcon_v1_wait_idle(struct nvkm_falcon *falcon) falcon 323 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_device *device = falcon->owner->device; falcon 326 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0); falcon 334 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_enable(struct nvkm_falcon *falcon) falcon 336 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_device *device = falcon->owner->device; falcon 339 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0); falcon 341 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_error(falcon->user, "Falcon mem scrubbing timeout\n"); falcon 345 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = falcon_v1_wait_idle(falcon); falcon 350 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x010, 0xff); falcon 356 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_disable(struct nvkm_falcon *falcon) falcon 359 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x014, 0xff); falcon 360 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c falcon_v1_wait_idle(falcon); falcon 381 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c struct nvkm_falcon *falcon; falcon 382 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL))) falcon 384 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon); falcon 35 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c return nvkm_falcon_v1_new(subdev, "GSP", gsp->addr, &gsp->falcon); falcon 42 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c nvkm_falcon_del(&gsp->falcon); falcon 140 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c return nvkm_falcon_v1_new(&pmu->subdev, "PMU", 0x10a000, &pmu->falcon); falcon 148 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c nvkm_falcon_del(&pmu->falcon); falcon 98 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_falcon *falcon = pmu->base.falcon; falcon 100 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); falcon 101 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); falcon 107 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_falcon *falcon = pmu->base.falcon; falcon 109 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); falcon 110 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); falcon 163 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_put(pmu->falcon, &pmu->subdev); falcon 172 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c struct nvkm_falcon *falcon = pmu->falcon; falcon 175 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c ret = nvkm_falcon_get(falcon, subdev); falcon 177 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_error(subdev, "cannot acquire %s falcon!\n", falcon->name); falcon 182 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001); falcon 183 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_wr32(falcon, 0x50c + (BUSY_SLOT * 0x10), 0x00000002); falcon 184 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c nvkm_falcon_wr32(falcon, 0x50c + (CLK_SLOT * 0x10), 0x00000003); falcon 781 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr_r352_load(struct nvkm_acr *_acr, struct nvkm_falcon *falcon, falcon 820 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0); falcon 823 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size, falcon 832 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, falcon 962 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c int falcon; falcon 981 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) { falcon 982 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c acr->falcon_state[falcon] = RESET; falcon 1000 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c int falcon; falcon 1031 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c for_each_set_bit(falcon, &falcon_mask, NVKM_SECBOOT_FALCON_END) falcon 1033 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c nvkm_secboot_falcon_name[falcon]); falcon 1153 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c addr_args = pmu->falcon->data.limit; falcon 129 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_args = pmu->falcon->data.limit; falcon 175 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c addr_args = sec->falcon->data.limit; falcon 99 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c addr_args = sec->falcon->data.limit; falcon 43 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c addr_args = pmu->falcon->data.limit; falcon 136 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c sb->halt_falcon = sb->boot_falcon = subdev->device->pmu->falcon; falcon 141 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c sb->boot_falcon = subdev->device->sec2->falcon; falcon 142 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c sb->halt_falcon = subdev->device->pmu->falcon; falcon 38 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c struct nvkm_falcon *falcon) falcon 46 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_falcon_get(falcon, subdev); falcon 53 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_put(falcon, subdev); falcon 62 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_falcon_reset(falcon); falcon 65 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_bind_context(falcon, gsb->inst); falcon 68 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = sb->acr->func->load(sb->acr, falcon, blob, vma->addr); falcon 75 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false); falcon 78 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); falcon 81 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_set_start_addr(falcon, start_address); falcon 82 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_start(falcon); falcon 83 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_falcon_wait_for_halt(falcon, 100); falcon 91 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c ret = nvkm_falcon_rd32(falcon, 0x040); falcon 95 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true); falcon 99 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c nvkm_falcon_put(falcon, subdev); falcon 52 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c struct nvkm_falcon *falcon; falcon 65 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c falcon = device->nvdec[0]->falcon; falcon 67 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_get(falcon, &sb->subdev); falcon 69 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c scrub_image = hs_ucode_load_blob(subdev, falcon, "nvdec/scrubber"); falcon 73 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_reset(falcon); falcon 74 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_bind_context(falcon, NULL); falcon 81 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_load_imem(falcon, scrub_data, lhdr->non_sec_code_off, falcon 84 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_load_imem(falcon, scrub_data + lhdr->apps[0], falcon 88 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_load_dmem(falcon, scrub_data + lhdr->data_dma_base, 0, falcon 93 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_set_start_addr(falcon, 0x0); falcon 94 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_start(falcon); falcon 96 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c ret = nvkm_falcon_wait_for_halt(falcon, 500); falcon 104 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_reset(falcon); falcon 115 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c nvkm_falcon_put(falcon, &sb->subdev); falcon 122 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c struct nvkm_falcon *falcon) falcon 133 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c return gm200_secboot_run_blob(sb, blob, falcon); falcon 34 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c hs_ucode_patch_signature(const struct nvkm_falcon *falcon, void *acr_image, falcon 58 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c if (falcon->debug) { falcon 71 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c hs_ucode_load_blob(struct nvkm_subdev *subdev, const struct nvkm_falcon *falcon, falcon 94 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/hs_ucode.c hs_ucode_patch_signature(falcon, acr_image, new_format); falcon 80 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c struct nvkm_falcon *falcon, u32 addr_args) falcon 82 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c struct nvkm_device *device = falcon->owner->device; falcon 87 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_falcon_load_dmem(falcon, buf, addr_args, sizeof(buf), 0); falcon 92 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_falcon_wr32(falcon, 0x10, 0xff); falcon 93 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_mc_intr_mask(device, falcon->owner->index, true); falcon 96 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c nvkm_falcon_start(falcon); falcon 113 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c ret = nvkm_msgqueue_new(img->ucode_desc.app_version, pmu->falcon, falcon 126 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c u32 addr_args = pmu->falcon->data.limit - NVKM_MSGQUEUE_CMDLINE_SIZE; falcon 129 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c ret = acr_ls_msgqueue_post_run(pmu->queue, pmu->falcon, addr_args); falcon 151 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c ret = nvkm_msgqueue_new(img->ucode_desc.app_version, sec->falcon, falcon 169 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_msgqueue.c ret = acr_ls_msgqueue_post_run(sec->queue, sec->falcon, addr_args); falcon 20 drivers/gpu/drm/tegra/falcon.c static void falcon_writel(struct falcon *falcon, u32 value, u32 offset) falcon 22 drivers/gpu/drm/tegra/falcon.c writel(value, falcon->regs + offset); falcon 25 drivers/gpu/drm/tegra/falcon.c int falcon_wait_idle(struct falcon *falcon) falcon 29 drivers/gpu/drm/tegra/falcon.c return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value, falcon 33 drivers/gpu/drm/tegra/falcon.c static int falcon_dma_wait_idle(struct falcon *falcon) falcon 37 drivers/gpu/drm/tegra/falcon.c return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value, falcon 41 drivers/gpu/drm/tegra/falcon.c static int falcon_copy_chunk(struct falcon *falcon, falcon 51 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, offset, FALCON_DMATRFMOFFS); falcon 52 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, base, FALCON_DMATRFFBOFFS); falcon 53 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, cmd, FALCON_DMATRFCMD); falcon 55 drivers/gpu/drm/tegra/falcon.c return falcon_dma_wait_idle(falcon); falcon 58 drivers/gpu/drm/tegra/falcon.c static void falcon_copy_firmware_image(struct falcon *falcon, falcon 61 drivers/gpu/drm/tegra/falcon.c u32 *firmware_vaddr = falcon->firmware.vaddr; falcon 71 drivers/gpu/drm/tegra/falcon.c daddr = dma_map_single(falcon->dev, firmware_vaddr, falcon 72 drivers/gpu/drm/tegra/falcon.c falcon->firmware.size, DMA_TO_DEVICE); falcon 73 drivers/gpu/drm/tegra/falcon.c err = dma_mapping_error(falcon->dev, daddr); falcon 75 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "failed to map firmware: %d\n", err); falcon 78 drivers/gpu/drm/tegra/falcon.c dma_sync_single_for_device(falcon->dev, daddr, falcon 79 drivers/gpu/drm/tegra/falcon.c falcon->firmware.size, DMA_TO_DEVICE); falcon 80 drivers/gpu/drm/tegra/falcon.c dma_unmap_single(falcon->dev, daddr, falcon->firmware.size, falcon 84 drivers/gpu/drm/tegra/falcon.c static int falcon_parse_firmware_image(struct falcon *falcon) falcon 86 drivers/gpu/drm/tegra/falcon.c struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.vaddr; falcon 91 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "incorrect firmware magic\n"); falcon 97 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "unsupported firmware version\n"); falcon 102 drivers/gpu/drm/tegra/falcon.c if (bin->size > falcon->firmware.size) { falcon 103 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "firmware image size inconsistency\n"); falcon 107 drivers/gpu/drm/tegra/falcon.c os = falcon->firmware.vaddr + bin->os_header_offset; falcon 109 drivers/gpu/drm/tegra/falcon.c falcon->firmware.bin_data.size = bin->os_size; falcon 110 drivers/gpu/drm/tegra/falcon.c falcon->firmware.bin_data.offset = bin->os_data_offset; falcon 111 drivers/gpu/drm/tegra/falcon.c falcon->firmware.code.offset = os->code_offset; falcon 112 drivers/gpu/drm/tegra/falcon.c falcon->firmware.code.size = os->code_size; falcon 113 drivers/gpu/drm/tegra/falcon.c falcon->firmware.data.offset = os->data_offset; falcon 114 drivers/gpu/drm/tegra/falcon.c falcon->firmware.data.size = os->data_size; falcon 119 drivers/gpu/drm/tegra/falcon.c int falcon_read_firmware(struct falcon *falcon, const char *name) falcon 124 drivers/gpu/drm/tegra/falcon.c err = request_firmware(&falcon->firmware.firmware, name, falcon->dev); falcon 131 drivers/gpu/drm/tegra/falcon.c int falcon_load_firmware(struct falcon *falcon) falcon 133 drivers/gpu/drm/tegra/falcon.c const struct firmware *firmware = falcon->firmware.firmware; falcon 136 drivers/gpu/drm/tegra/falcon.c falcon->firmware.size = firmware->size; falcon 139 drivers/gpu/drm/tegra/falcon.c falcon->firmware.vaddr = falcon->ops->alloc(falcon, firmware->size, falcon 140 drivers/gpu/drm/tegra/falcon.c &falcon->firmware.paddr); falcon 141 drivers/gpu/drm/tegra/falcon.c if (IS_ERR(falcon->firmware.vaddr)) { falcon 142 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "DMA memory mapping failed\n"); falcon 143 drivers/gpu/drm/tegra/falcon.c return PTR_ERR(falcon->firmware.vaddr); falcon 147 drivers/gpu/drm/tegra/falcon.c falcon_copy_firmware_image(falcon, firmware); falcon 150 drivers/gpu/drm/tegra/falcon.c err = falcon_parse_firmware_image(falcon); falcon 152 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "failed to parse firmware image\n"); falcon 157 drivers/gpu/drm/tegra/falcon.c falcon->firmware.firmware = NULL; falcon 162 drivers/gpu/drm/tegra/falcon.c falcon->ops->free(falcon, falcon->firmware.size, falcon 163 drivers/gpu/drm/tegra/falcon.c falcon->firmware.paddr, falcon->firmware.vaddr); falcon 168 drivers/gpu/drm/tegra/falcon.c int falcon_init(struct falcon *falcon) falcon 171 drivers/gpu/drm/tegra/falcon.c if (!falcon->ops || !falcon->ops->alloc || !falcon->ops->free) falcon 174 drivers/gpu/drm/tegra/falcon.c falcon->firmware.vaddr = NULL; falcon 179 drivers/gpu/drm/tegra/falcon.c void falcon_exit(struct falcon *falcon) falcon 181 drivers/gpu/drm/tegra/falcon.c if (falcon->firmware.firmware) { falcon 182 drivers/gpu/drm/tegra/falcon.c release_firmware(falcon->firmware.firmware); falcon 183 drivers/gpu/drm/tegra/falcon.c falcon->firmware.firmware = NULL; falcon 186 drivers/gpu/drm/tegra/falcon.c if (falcon->firmware.vaddr) { falcon 187 drivers/gpu/drm/tegra/falcon.c falcon->ops->free(falcon, falcon->firmware.size, falcon 188 drivers/gpu/drm/tegra/falcon.c falcon->firmware.paddr, falcon 189 drivers/gpu/drm/tegra/falcon.c falcon->firmware.vaddr); falcon 190 drivers/gpu/drm/tegra/falcon.c falcon->firmware.vaddr = NULL; falcon 194 drivers/gpu/drm/tegra/falcon.c int falcon_boot(struct falcon *falcon) falcon 200 drivers/gpu/drm/tegra/falcon.c if (!falcon->firmware.vaddr) falcon 203 drivers/gpu/drm/tegra/falcon.c err = readl_poll_timeout(falcon->regs + FALCON_DMACTL, value, falcon 210 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, 0, FALCON_DMACTL); falcon 213 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, (falcon->firmware.paddr + falcon 214 drivers/gpu/drm/tegra/falcon.c falcon->firmware.bin_data.offset) >> 8, falcon 218 drivers/gpu/drm/tegra/falcon.c for (offset = 0; offset < falcon->firmware.data.size; offset += 256) falcon 219 drivers/gpu/drm/tegra/falcon.c falcon_copy_chunk(falcon, falcon 220 drivers/gpu/drm/tegra/falcon.c falcon->firmware.data.offset + offset, falcon 224 drivers/gpu/drm/tegra/falcon.c falcon_copy_chunk(falcon, falcon->firmware.code.offset, falcon 228 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) | falcon 235 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) | falcon 243 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, FALCON_ITFEN_MTHDEN | falcon 248 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC); falcon 249 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL); falcon 251 drivers/gpu/drm/tegra/falcon.c err = falcon_wait_idle(falcon); falcon 253 drivers/gpu/drm/tegra/falcon.c dev_err(falcon->dev, "Falcon boot failed due to timeout\n"); falcon 260 drivers/gpu/drm/tegra/falcon.c void falcon_execute_method(struct falcon *falcon, u32 method, u32 data) falcon 262 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET); falcon 263 drivers/gpu/drm/tegra/falcon.c falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA); falcon 77 drivers/gpu/drm/tegra/falcon.h struct falcon; falcon 80 drivers/gpu/drm/tegra/falcon.h void *(*alloc)(struct falcon *falcon, size_t size, falcon 82 drivers/gpu/drm/tegra/falcon.h void (*free)(struct falcon *falcon, size_t size, falcon 116 drivers/gpu/drm/tegra/falcon.h int falcon_init(struct falcon *falcon); falcon 117 drivers/gpu/drm/tegra/falcon.h void falcon_exit(struct falcon *falcon); falcon 118 drivers/gpu/drm/tegra/falcon.h int falcon_read_firmware(struct falcon *falcon, const char *firmware_name); falcon 119 drivers/gpu/drm/tegra/falcon.h int falcon_load_firmware(struct falcon *falcon); falcon 120 drivers/gpu/drm/tegra/falcon.h int falcon_boot(struct falcon *falcon); falcon 121 drivers/gpu/drm/tegra/falcon.h void falcon_execute_method(struct falcon *falcon, u32 method, u32 data); falcon 122 drivers/gpu/drm/tegra/falcon.h int falcon_wait_idle(struct falcon *falcon); falcon 31 drivers/gpu/drm/tegra/vic.c struct falcon falcon; falcon 131 drivers/gpu/drm/tegra/vic.c err = falcon_boot(&vic->falcon); falcon 135 drivers/gpu/drm/tegra/vic.c hdr = vic->falcon.firmware.vaddr; falcon 137 drivers/gpu/drm/tegra/vic.c hdr = vic->falcon.firmware.vaddr + falcon 141 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1); falcon 142 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, falcon 144 drivers/gpu/drm/tegra/vic.c falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET, falcon 145 drivers/gpu/drm/tegra/vic.c (vic->falcon.firmware.paddr + fce_bin_data_offset) falcon 148 drivers/gpu/drm/tegra/vic.c err = falcon_wait_idle(&vic->falcon); falcon 160 drivers/gpu/drm/tegra/vic.c static void *vic_falcon_alloc(struct falcon *falcon, size_t size, falcon 163 drivers/gpu/drm/tegra/vic.c struct tegra_drm *tegra = falcon->data; falcon 168 drivers/gpu/drm/tegra/vic.c static void vic_falcon_free(struct falcon *falcon, size_t size, falcon 171 drivers/gpu/drm/tegra/vic.c struct tegra_drm *tegra = falcon->data; falcon 263 drivers/gpu/drm/tegra/vic.c if (vic->falcon.data) falcon 266 drivers/gpu/drm/tegra/vic.c vic->falcon.data = vic->client.drm; falcon 268 drivers/gpu/drm/tegra/vic.c err = falcon_read_firmware(&vic->falcon, vic->config->firmware); falcon 272 drivers/gpu/drm/tegra/vic.c err = falcon_load_firmware(&vic->falcon); falcon 279 drivers/gpu/drm/tegra/vic.c vic->falcon.data = NULL; falcon 411 drivers/gpu/drm/tegra/vic.c vic->falcon.dev = dev; falcon 412 drivers/gpu/drm/tegra/vic.c vic->falcon.regs = vic->regs; falcon 413 drivers/gpu/drm/tegra/vic.c vic->falcon.ops = &vic_falcon_ops; falcon 415 drivers/gpu/drm/tegra/vic.c err = falcon_init(&vic->falcon); falcon 451 drivers/gpu/drm/tegra/vic.c falcon_exit(&vic->falcon); falcon 473 drivers/gpu/drm/tegra/vic.c falcon_exit(&vic->falcon); falcon 130 drivers/video/fbdev/atafb.c } falcon; falcon 142 drivers/video/fbdev/atafb.c #define HHT hw.falcon.hht falcon 143 drivers/video/fbdev/atafb.c #define HBB hw.falcon.hbb falcon 144 drivers/video/fbdev/atafb.c #define HBE hw.falcon.hbe falcon 145 drivers/video/fbdev/atafb.c #define HDB hw.falcon.hdb falcon 146 drivers/video/fbdev/atafb.c #define HDE hw.falcon.hde falcon 147 drivers/video/fbdev/atafb.c #define HSS hw.falcon.hss falcon 148 drivers/video/fbdev/atafb.c #define VFT hw.falcon.vft falcon 149 drivers/video/fbdev/atafb.c #define VBB hw.falcon.vbb falcon 150 drivers/video/fbdev/atafb.c #define VBE hw.falcon.vbe falcon 151 drivers/video/fbdev/atafb.c #define VDB hw.falcon.vdb falcon 152 drivers/video/fbdev/atafb.c #define VDE hw.falcon.vde falcon 153 drivers/video/fbdev/atafb.c #define VSS hw.falcon.vss falcon 876 drivers/video/fbdev/atafb.c if (par->hw.falcon.mono) { falcon 881 drivers/video/fbdev/atafb.c } else if (par->hw.falcon.f_shift & 0x100) { falcon 945 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x400; falcon 946 drivers/video/fbdev/atafb.c par->hw.falcon.st_shift = 0x200; falcon 949 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x000; falcon 950 drivers/video/fbdev/atafb.c par->hw.falcon.st_shift = 0x100; falcon 953 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x000; falcon 954 drivers/video/fbdev/atafb.c par->hw.falcon.st_shift = 0x000; falcon 957 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x010; falcon 960 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x100; /* hicolor, no overlay */ falcon 963 drivers/video/fbdev/atafb.c par->hw.falcon.bpp = bpp; falcon 990 drivers/video/fbdev/atafb.c par->hw.falcon.ste_mode = bpp == 2; falcon 991 drivers/video/fbdev/atafb.c par->hw.falcon.mono = bpp == 1; falcon 1001 drivers/video/fbdev/atafb.c if (par->hw.falcon.ste_mode) falcon 1028 drivers/video/fbdev/atafb.c par->hw.falcon.line_width = bpp * xres / 16; falcon 1029 drivers/video/fbdev/atafb.c par->hw.falcon.line_offset = bpp * (xres_virtual - xres) / 16; falcon 1041 drivers/video/fbdev/atafb.c par->hw.falcon.ste_mode = 1; falcon 1042 drivers/video/fbdev/atafb.c par->hw.falcon.f_shift = 0x000; falcon 1043 drivers/video/fbdev/atafb.c par->hw.falcon.st_shift = 0x200; falcon 1178 drivers/video/fbdev/atafb.c par->hw.falcon.vid_control = mon_type | f030_bus_width; falcon 1180 drivers/video/fbdev/atafb.c par->hw.falcon.vid_control |= VCO_SHORTOFFS; /* base_offset 64 */ falcon 1182 drivers/video/fbdev/atafb.c par->hw.falcon.vid_control |= VCO_HSYPOS; falcon 1184 drivers/video/fbdev/atafb.c par->hw.falcon.vid_control |= VCO_VSYPOS; falcon 1186 drivers/video/fbdev/atafb.c par->hw.falcon.vid_control |= pclock->control_mask; falcon 1188 drivers/video/fbdev/atafb.c par->hw.falcon.sync = pclock->sync_mask | 0x2; falcon 1190 drivers/video/fbdev/atafb.c par->hw.falcon.vid_mode = (2 / plen) << 2; falcon 1192 drivers/video/fbdev/atafb.c par->hw.falcon.vid_mode |= VMO_DOUBLE; falcon 1194 drivers/video/fbdev/atafb.c par->hw.falcon.vid_mode |= VMO_INTER; falcon 1218 drivers/video/fbdev/atafb.c prescale = hxx_prescale(&par->hw.falcon); falcon 1219 drivers/video/fbdev/atafb.c base_off = par->hw.falcon.vid_control & VCO_SHORTOFFS ? 64 : 128; falcon 1225 drivers/video/fbdev/atafb.c if (par->hw.falcon.f_shift & 0x100) { falcon 1232 drivers/video/fbdev/atafb.c if (par->hw.falcon.ste_mode) falcon 1362 drivers/video/fbdev/atafb.c par->hw.falcon.xoffset = 0; falcon 1376 drivers/video/fbdev/atafb.c struct falcon_hw *hw = &par->hw.falcon; falcon 1538 drivers/video/fbdev/atafb.c struct falcon_hw *hw = &par->hw.falcon; falcon 1590 drivers/video/fbdev/atafb.c f_new_mode = par->hw.falcon; falcon 1646 drivers/video/fbdev/atafb.c videl.xoffset = current_par.hw.falcon.xoffset; falcon 1647 drivers/video/fbdev/atafb.c shifter_f030.off_next = current_par.hw.falcon.line_offset; falcon 1663 drivers/video/fbdev/atafb.c par->hw.falcon.xoffset = var->xoffset & 15; falcon 1665 drivers/video/fbdev/atafb.c par->hw.falcon.xoffset = 0; falcon 1668 drivers/video/fbdev/atafb.c par->hw.falcon.line_offset = bpp * falcon 1670 drivers/video/fbdev/atafb.c if (par->hw.falcon.xoffset) falcon 1671 drivers/video/fbdev/atafb.c par->hw.falcon.line_offset -= bpp; falcon 1672 drivers/video/fbdev/atafb.c xoffset = var->xoffset - par->hw.falcon.xoffset; falcon 3182 drivers/video/fbdev/atafb.c fb_info.pseudo_palette = current_par.hw.falcon.pseudo_palette;