f3 162 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f3; /* preserved */ f3 131 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_SWITCH_STACK_F3_OFFSET, offsetof (struct switch_stack, f3)); f3 45 arch/ia64/kernel/entry.h .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \ f3 232 arch/ia64/kernel/unaligned.c RSW(f2), RSW(f3), RSW(f4), RSW(f5), f3 114 arch/mips/include/asm/asmmacro.h sdc1 $f3, THREAD_FPR3(\thread) f3 173 arch/mips/include/asm/asmmacro.h ldc1 $f3, THREAD_FPR3(\thread) f3 40 arch/mips/include/asm/fpregdef.h #define fv1f $f3 f3 99 arch/mips/include/asm/fpregdef.h #define ft13 $f3 f3 1418 arch/mips/math-emu/cp1emu.c #define DEF3OP(name, p, f1, f2, f3) \ f3 1428 arch/mips/math-emu/cp1emu.c s = f3(s); \ f3 25 arch/nds32/math-emu/fpuemu.c #define DEF3OPNEG(name, p, f1, f2, f3) \ f3 30 arch/nds32/math-emu/fpuemu.c f3(ft, ft); \ f3 1383 arch/sparc/include/asm/hypervisor.h unsigned long f3; /* Entry specific */ f3 72 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ f3 76 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) f3 78 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ f3 82 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ f3 85 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f3 90 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ f3 94 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f3 99 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ f3 104 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f3 109 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ f3 115 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f3 120 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ f3 127 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f3 132 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 140 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f3 145 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 165 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ f3 169 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3) f3 171 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ f3 175 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ f3 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f3 182 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ f3 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f3 190 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ f3 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f3 199 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ f3 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f3 209 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ f3 239 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ f3 243 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) f3 245 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ f3 249 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f3 256 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f3 264 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f3 273 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f3 283 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f3 294 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f3 306 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f3 320 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f3 338 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f3 361 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ f3 386 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \ f3 389 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f3, v3); } f3 243 drivers/gpu/drm/msm/edp/edp_ctrl.c goto f3; f3 249 drivers/gpu/drm/msm/edp/edp_ctrl.c goto f3; f3 265 drivers/gpu/drm/msm/edp/edp_ctrl.c f3: f3 29 drivers/media/tuners/m88rs6000t.c u8 N, f0 = 0, f1 = 0, f2 = 0, f3 = 0; f3 68 drivers/media/tuners/m88rs6000t.c f3 = 0; f3 74 drivers/media/tuners/m88rs6000t.c f3 = 0; f3 80 drivers/media/tuners/m88rs6000t.c f3 = div - f0 - f1 - f2; f3 86 drivers/media/tuners/m88rs6000t.c f3 = 16; f3 95 drivers/media/tuners/m88rs6000t.c if (f3 == 16) f3 96 drivers/media/tuners/m88rs6000t.c f3 = 0; f3 104 drivers/media/tuners/m88rs6000t.c reg1E = ((f3 << 4) + f2) & 0xFF; f3 563 drivers/net/wireless/ath/ath9k/ar9003_calib.c f3 = sin_2phi_1 - sin_2phi_2, f3 569 drivers/net/wireless/ath/ath9k/ar9003_calib.c f2 = ((f1 >> 3) * (f1 >> 3) + (f3 >> 3) * (f3 >> 3)) >> 9; f3 577 drivers/net/wireless/ath/ath9k/ar9003_calib.c mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0); f3 579 drivers/net/wireless/ath/ath9k/ar9003_calib.c phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0); f3 51 drivers/pinctrl/pinctrl-falcon.c #define MFP_FALCON(a, f0, f1, f2, f3) \ f3 59 drivers/pinctrl/pinctrl-falcon.c FALCON_MUX_##f3, \ f3 211 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f3 216 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f3 223 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f3 228 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f3 63 drivers/pinctrl/pinctrl-xway.c #define MFP_XWAY(a, f0, f1, f2, f3) \ f3 71 drivers/pinctrl/pinctrl-xway.c XWAY_MUX_##f3, \ f3 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f3 228 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f3, \ f3 334 drivers/pinctrl/qcom/pinctrl-apq8084.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f3 343 drivers/pinctrl/qcom/pinctrl-apq8084.c APQ_MUX_##f3, \ f3 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f3 235 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f3, \ f3 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f3 180 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f3, \ f3 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 30 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f3, \ f3 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f3 214 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f3, \ f3 385 drivers/pinctrl/qcom/pinctrl-msm8660.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f3 394 drivers/pinctrl/qcom/pinctrl-msm8660.c MSM_MUX_##f3, \ f3 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 305 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f3, \ f3 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f3 353 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f3, \ f3 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f3 29 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f3, \ f3 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 31 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f3, \ f3 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 33 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f3, \ f3 335 drivers/pinctrl/qcom/pinctrl-msm8x74.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f3 344 drivers/pinctrl/qcom/pinctrl-msm8x74.c MSM_MUX_##f3, \ f3 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 41 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f3, \ f3 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 39 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f3, \ f3 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 45 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f3, \ f3 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f3 34 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f3, \ f3 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f3 41 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f3, \ f3 423 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 f3 424 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 f3 386 drivers/pinctrl/sh-pfc/pfc-r8a77995.c #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 f3 1550 drivers/pinctrl/tegra/pinctrl-tegra114.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ f3 1559 drivers/pinctrl/tegra/pinctrl-tegra114.c TEGRA_MUX_##f3, \ f3 1719 drivers/pinctrl/tegra/pinctrl-tegra124.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \ f3 1728 drivers/pinctrl/tegra/pinctrl-tegra124.c TEGRA_MUX_##f3, \ f3 110 drivers/pinctrl/tegra/pinctrl-tegra194.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \ f3 120 drivers/pinctrl/tegra/pinctrl-tegra194.c TEGRA_MUX_##f3, \ f3 1971 drivers/pinctrl/tegra/pinctrl-tegra20.c #define MUX_PG(pg_name, f0, f1, f2, f3, \ f3 1981 drivers/pinctrl/tegra/pinctrl-tegra20.c TEGRA_MUX_ ## f3, \ f3 1278 drivers/pinctrl/tegra/pinctrl-tegra210.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \ f3 1289 drivers/pinctrl/tegra/pinctrl-tegra210.c TEGRA_MUX_##f3, \ f3 2111 drivers/pinctrl/tegra/pinctrl-tegra30.c #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ f3 2120 drivers/pinctrl/tegra/pinctrl-tegra30.c TEGRA_MUX_##f3, \ f3 287 drivers/s390/block/dasd_eckd.h __u16 f3; f3 292 drivers/s390/block/dasd_eckd.h __u8 f3; f3 323 mm/kasan/generic.c DEFINE_ASAN_SET_SHADOW(f3); f3 17 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f3, 21),