exynos_smc         45 arch/arm/mach-exynos/firmware.c 			exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
exynos_smc         47 arch/arm/mach-exynos/firmware.c 			exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
exynos_smc         50 arch/arm/mach-exynos/firmware.c 			exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
exynos_smc         53 arch/arm/mach-exynos/firmware.c 		exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
exynos_smc         70 arch/arm/mach-exynos/firmware.c 	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
exynos_smc        116 arch/arm/mach-exynos/firmware.c 	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
exynos_smc        163 arch/arm/mach-exynos/firmware.c 				exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
exynos_smc        169 arch/arm/mach-exynos/firmware.c 		exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
exynos_smc        173 arch/arm/mach-exynos/firmware.c 		exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
exynos_smc        183 arch/arm/mach-exynos/firmware.c 	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
exynos_smc        185 arch/arm/mach-exynos/firmware.c 	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
exynos_smc         37 arch/arm/mach-exynos/smc.h extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
exynos_smc        347 arch/arm/mach-exynos/suspend.c 		exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +
exynos_smc        489 arch/arm/mach-exynos/suspend.c 		exynos_smc(SMC_CMD_REG,