ep93xx_syscon_swlocked_write  256 arch/arm/mach-ep93xx/clock.c 				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
ep93xx_syscon_swlocked_write  287 arch/arm/mach-ep93xx/clock.c 				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
ep93xx_syscon_swlocked_write  354 arch/arm/mach-ep93xx/clock.c 	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
ep93xx_syscon_swlocked_write  432 arch/arm/mach-ep93xx/clock.c 	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
ep93xx_syscon_swlocked_write  441 arch/arm/mach-ep93xx/clock.c 		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
ep93xx_syscon_swlocked_write  444 arch/arm/mach-ep93xx/clock.c 		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
ep93xx_syscon_swlocked_write  459 arch/arm/mach-ep93xx/clock.c 		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
ep93xx_syscon_swlocked_write  462 arch/arm/mach-ep93xx/clock.c 		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
ep93xx_syscon_swlocked_write  465 arch/arm/mach-ep93xx/clock.c 		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
ep93xx_syscon_swlocked_write  688 arch/arm/mach-ep93xx/core.c 	ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
ep93xx_syscon_swlocked_write  198 arch/arm/mach-ep93xx/soc.h void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);