ep93xx_ac97_write_reg  138 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
ep93xx_ac97_write_reg  139 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
ep93xx_ac97_write_reg  163 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97S2DATA, val);
ep93xx_ac97_write_reg  164 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
ep93xx_ac97_write_reg  166 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
ep93xx_ac97_write_reg  185 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
ep93xx_ac97_write_reg  186 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
ep93xx_ac97_write_reg  203 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97GCR, 0);
ep93xx_ac97_write_reg  204 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
ep93xx_ac97_write_reg  205 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
ep93xx_ac97_write_reg  210 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
ep93xx_ac97_write_reg  211 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
ep93xx_ac97_write_reg  237 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97IM, mask);
ep93xx_ac97_write_reg  268 sound/soc/cirrus/ep93xx-ac97.c 			ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
ep93xx_ac97_write_reg  277 sound/soc/cirrus/ep93xx-ac97.c 			ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
ep93xx_ac97_write_reg  304 sound/soc/cirrus/ep93xx-ac97.c 			ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
ep93xx_ac97_write_reg  307 sound/soc/cirrus/ep93xx-ac97.c 			ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
ep93xx_ac97_write_reg  424 sound/soc/cirrus/ep93xx-ac97.c 	ep93xx_ac97_write_reg(info, AC97GCR, 0);