CH_EN 100 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); CH_EN 101 drivers/clocksource/timer-atcpit100.c writel(val | CH1TMR0EN, base + CH_EN); CH_EN 108 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); CH_EN 109 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, base + CH_EN); CH_EN 117 drivers/clocksource/timer-atcpit100.c val = readl(base + CH_EN); CH_EN 118 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, base + CH_EN); CH_EN 127 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); CH_EN 128 drivers/clocksource/timer-atcpit100.c writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN); CH_EN 130 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); CH_EN 158 drivers/clocksource/timer-atcpit100.c val = readl(timer_of_base(to) + CH_EN); CH_EN 159 drivers/clocksource/timer-atcpit100.c writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN); CH_EN 148 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); CH_EN 149 drivers/dma/dw/core.c while (dma_readl(dw, CH_EN) & dwc->mask) CH_EN 172 drivers/dma/dw/core.c channel_set_bit(dw, CH_EN, dwc->mask); CH_EN 186 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { CH_EN 221 drivers/dma/dw/core.c channel_set_bit(dw, CH_EN, dwc->mask); CH_EN 274 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { CH_EN 987 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { CH_EN 1028 drivers/dma/dw/core.c BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); CH_EN 1161 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); CH_EN 1257 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); CH_EN 85 drivers/dma/dw/regs.h DW_REG(CH_EN); CH_EN 86 drivers/dma/idma64.c channel_clear_bit(idma64, CH_EN, idma64c->mask); CH_EN 102 drivers/dma/idma64.c channel_set_bit(idma64, CH_EN, idma64c->mask);